According to JEDEC’s roadmap, DDR3 now comes in two speed grades: 1,333- and 1,600-MHz. An 1,866-MHz version is also on the roadmap. Following DDR3, Elpida, Hynix, Micron and Samsung are developing monolithic parts based on the next-generation interface — DDR4.
The first DDR4 DRAMs will come in 4-Gbit densities and 2xnm processes. The devices will operate at 2,133- and 2,400-MHz, which are slated for delivery in 2014 and 2015, respectively, according to the JEDEC roadmap. A 3,200-MHz and 16-Gbit version is due out in 2020.
Based on a 1.2-volt technology and a 16-bank architecture, DDR4 is expected to be about 30 percent to 40 percent lower power than DDR3. DDR4 also features VDDQ DQ termination, a 500,000 page size for x4 devices, new RAS features and error correction on the SODIMM using a common connector.
Also in 2014, the first 3D-based DDR4 chips are expected to appear in a 20nm, two-stacked configuration, according to the JEDEC roadmap. Four- and eight-stacked DDR4 versions are due out in 2016 and 2017.
Some JEDEC members are floating a 3D technology called high-bandwidth, which stacks DRAM on top of a logic device in a master-slave configuration. This is basically a server version of the so-called wide I/O memory scheme. Geared for handhelds, wide I/O DRAM is a four-channel, 128-lane technology said to enable a bandwidth of up to 12 Gbytes/s.
Roadmap debate
Samsung has other ideas about the DRAM roadmap. At the event, Jang Seok Choi, senior engineer at Samsung Semiconductor, presented a slide that tipped Samsung’s aggressive roadmap. As part of the plan, a 1.25-volt version of DDR3 would appear in 2011, followed by DDR3-based 3D TSV devices at 1,866-MHz in 2012, following by DDR4 in 2013.