Predict: The Next Generation Console Tech

[Proelite]

Ranger, do you know what's the largest die size that you can dedicate to a SOC for a console?

 

[Tahir2]

The RSX die size I was able to google was 240 mm^2, Xenos figure was 182 mm^2 parent die and 80 mm^2 daughter die (262 mm^2 total) (all on 90 nm).

GTX580 is 520 mm^2, HD 6970 is 389 mm^2. And that's on 40nm.

So if they have roughly the same budgets as last time, you could probably fit a GTX 580 or a HD 6970 in those budgets, on 28nm (I'm assuming a rough halving of die size per node). Or, a mid range of the next gen on 22nm, so to speak.

On 22nm, on the same ~240 mm^2 budget, you could probably fit a high end Southern Islands, or Nvidia Kepler chip in there. Sort of, leaving out the EDRAM to some extent, or leaving it off to the side, or squeezing it in somehow or other, depending, and depending how much you want. Of course keeping in mind, Kepler and Southern Islands will be last gen chip by the time these consoles launch. (or again, instead of high end Kepler/SI, you could get a mid range HD9xx or Nvidia Kepler+1 for the same effect).

For EDRAM, well if you got 10MB on 90nm, 20 on 65m, 40 on 40, 80 on 28nm, 160 mb on 22nm? You could save some space there it seems, I dont think you need 160 MB am I right? So perhaps you could fit your EDRAM in a 40 mm^2 die this time, if you "only" want 80 MB of it. That is if EDRAM still makes sense next gen, I'm unclear.

I would say the one fly in all these calculations is, what if the console manufacturers next gen are willing to increase their die budget? Say up to 300 mm^2, or even higher, for the GPU?

But yeah, high end AMD HD7XXX series or mid range HD9XXX (I use 9XXX because 8XXX will just be the refresh card) doesnt sound bad at all. That's IF we get to 22nm for next gen consoles. Subtract a gen from the GPU class otherwise .

It also becomes questionable if HD 9XXX would actually be out in time. There was a little over a year between HD5870 and HD6970, both on 40nm. If Southern Islands hits in first quarter 2012, the HD8XXX would hit in 1Q 2013, and perhaps the HD9XXX in 1Q 2014 if all goes well. Again, you'd be straddling some things. But I guess for our purposes it doesnt matter to much if you saw a high end HD8XXX, or a mid range HD9XXX in the console. They should perform similarly.

So yeah actually, I think that's pretty reasonable. on 28nm you might be looking at a HD6970 performance-class chip (in presumably next box here since we know their AMD connection). On 22nm you would be looking at a high end Southern Islands performance-class chip.

Unless that's not how it works out at all, heh.

It is quite likely the choice of GPU and CPU will be made many months in advance. A proven or custom design to fit certain characteristics will be the most manufacturers of consoles can work with. Unless they want another round of RRoD and YLoD.

So back to the one year thing, last time it bought PS3 the Blu-ray player - this time maybe something exotic like HMC (Hybrid Memory Cube)?

I realise I just contradicted myself there with regards to using "mature" technology.. but HMC looks pretty snazzy, excellent performance and low power consumption the only thing holding it back is cost and the fact it doesn't quite exist yet for the mass market.

 

[Blazkowicz]

that hybrid memory cube reminds me of X360's daughter die, I believe it could be used in such specialized ways at first. or it could be used as a processor that applies network rules and do network things with 10 gigabit ethernet connections.

it's a good deal interesting but we don't know yet if a 100W GPU with stacked memory is possible, it's probably not and requires a significant cooling breakthrough.

 

[MarkoIt]

...

28nm is ramping up just now, when was suppose to launch in Q4 2010 (TMSC).
For a fall 2013 console, a 20nm is out of question: too costly, and it won't have enough yields for launching a console. Same reason why CPU is going to be 32nm. IBM hasn't even used yet!

https://www.power.org/events/2010_ISSCC/Wire_Speed_Presentation_5.5_-_Final4.pdf

Looking at the die-shot, it's seems that almost half of space is used by accellerators and network.. with those out, at 32nm we would have a 160mm^2 chip, with 16 cores and 64 threads.

 

[liolio]

Ranger I believe you have the wrong numbers, it's tough to find the proper figures (I tried) as it's so old... Even here on B3D articles data seems wrong.
Xenos main die was ~232 millions transistors, @90 nm you packed really close to 1 million transistors per mm² (on average). Most likely the correct figures should look something like:
230mm² xenos
100mm² daughter die
+300mm² RSX

There is no way that 300millions transistors fit in 240mm² (RSX) and 232 in 170mm². Data are wrong and not a match for GPU of the same period using the same process (90nm).
Both systems had overall a silicon budget north of 500 mm².

 

[AlNom]

+300mm² RSX

RSX was measured to be around 240mm^2. It's bigger than G71, which was 191mm^2. The larger die size is due to a number of things including disabled ALUs, larger texture cache, and probably XDR I/O.

RSX had 28 ALUs vs 24 in G71. Texture cache was increased/doubled IIRC, though I don't know how much physical space that ultimately takes up. It just adds to the layout. There'll be some physical stuff needed for interfacing to XDR, though I suppose that would partially replace the 128-bit GDDR3 interface that would have made G71 256-bit.

 

[Rangers]

Ranger I believe you have the wrong numbers, it's tough to find the proper figures (I tried) as it's so old... Even here on B3D articles data seems wrong.
Xenos main die was ~232 millions transistors, @90 nm you packed really close to 1 million transistors per mm² (on average). Most likely the correct figures should look something like:
230mm² xenos
100mm² daughter die
+300mm² RSX

There is no way that 300millions transistors fit in 240mm² (RSX) and 232 in 170mm². Data are wrong and not a match for GPU of the same period using the same process (90nm).
Both systems had overall a silicon budget north of 500 mm².

I got the figures from supposed actual measurements. The Xenos figure from here http://www.anandtech.com/show/2682/4

 

[liolio]

RSX was measured to be around 240mm^2. It's bigger than G71, which was 191mm^2. The larger die size is due to a number of things including disabled ALUs, larger texture cache, and probably XDR I/O.

RSX had 28 ALUs vs 24 in G71. Texture cache was increased/doubled IIRC, though I don't know how much physical space that ultimately takes up. It just adds to the layout. There'll be some physical stuff needed for interfacing to XDR, though I suppose that would partially replace the 128-bit GDDR3 interface that would have made G71 256-bit.

I got the figures from supposed actual measurements. The Xenos figure from here http://www.anandtech.com/show/2682/4

Sorry but it's the wrong data or for the wrong process.
Ranger I read this while researching proper measurement. He's wrong.
Alstrong it's the same I don't know which process were use for G71 but the data doesn't add up (and the article in B3D about evolution/shrinks of nowadays systems seems confused too).

Simply look at the transistor density for Xenon and the Cell, mostly 1 million transistor per mm² using SOI 90 nm process. Now look at the density for Xenos and RSX it doesn't add up at all. Even if TMSC process was densier the disparity is way too great (1million/mm² vs 136millions, +33% and Cell is pretty well packed).

Sorry prior I posted I went over multiple pages of google results without finding what I wanted still I'm sure the data I gave from memory here (add or remove abit that's it) have been used multiple times here (I've no time for searching now, may be latter).
And I'm sure (memory but still) that the 80mm² for the xenos daughter die is the data using NEC 80 nm process.

Sorry but it looks like bad information has spread as the topic is old may further research on google could do the trick. Or searching this very forum I'm sure this data has been used before and there is a confusion between the process used.

EDIT
I was further researching the topic but I really have to go now, I will dig further latter.

EDIT 2
I could not stand it I search for a picture of a 360 motherboard from 2005 to find out that I was... wrong... Gross paint measurements shows that the xenos is barely bigger than Xenon.
Damned the figure I gave (as well as those Joshua gave have been use countless time without anybody correcting them... Damned I spread misinformation on the internet

 

[AlNom]

I'm not sure what the problem is on your end, but you can't directly equate RSX and G71. They are not the same chip. There are a number of changes and additions to G71 that I've already listed that would increase the die size of G71, and yes, this both at 90nm.

G71 was 278 million transistors and fit into 196mm^2 (Techreport). -> 1.41MT/mm^2
According to Anandtech, Xenos mother die is 182mm^2 with 232 MTs. ->1.27MT/mm^2
Daughter die is 100MT for 80mm^2 ala Anand. ->1.25MT/mm^2

I'm not sure I understand your density calculations being so difficult here.

We don't know how many more transistors make up the extra 4 ALUs, extra texture cache or the XDR interface, but it's apparently enough to bloat up G71 to 240mm^2.

Target clock speeds are going to have an impact on pipeline lengths and thus transistor density/counts as well. Afterall, there are good reasons why you don't hit ideal scaling when jumping nodes. When Xenos went from 90nm to 65nm, the density was nowhere near double.

 

[liolio]

Spoiler

I'm not sure what the problem is on your end, but you can't directly equate RSX and G71. They are not the same chip. There are a number of changes and additions to G71 that I've already listed that would increase the die size of G71, and yes, this both at 90nm.

G71 was 278 million transistors and fit into 196mm^2 (Techreport). -> 1.41MT/mm^2
According to Anandtech, Xenos mother die is 182mm^2 with 232 MTs. ->1.27MT/mm^2
Daughter die is 100MT for 80mm^2 ala Anand. ->1.25MT/mm^2

I'm not sure I understand your density calculations being so difficult here.

We don't know how many more transistors make up the extra 4 ALUs, extra texture cache or the XDR interface, but it's apparently enough to bloat up G71 to 240mm^2.

Target clock speeds are going to have an impact on pipeline lengths and thus transistor density/counts as well. Afterall, there are good reasons why you don't hit ideal scaling when jumping nodes. When Xenos went from 90nm to 65nm, the density was nowhere near double.

No more issue, I realized that the rule of thumb which worked pretty well for CPU (1million transistors /mm²) doesn't apply to bulk 90nm process. I believed for almost 7 years that the GPUs nowadays systems were significantly bigger than they really are (not that important still got he number of transistors right). That's it not much to say at least I was not alone I saw these wrong data used more than once and not only by me (as Joshua proved last page).

Anyway let's forget and clear my memory from this BS

 

[Proelite]

http://msnerd.tumblr.com/post/11725284513/rhythm

Interesting rumors.

 

[3dcgi]

The RSX die size I was able to google was 240 mm^2, Xenos figure was 182 mm^2 parent die and 80 mm^2 daughter die (262 mm^2 total) (all on 90 nm).

GTX580 is 520 mm^2, HD 6970 is 389 mm^2. And that's on 40nm.

Anand must have measured Xenos incorrectly. With a ruler I measured the parent die of C1 to be 13.5mm x 13mm or 175.5 so their 182 figure is probably correct. The daughter die is 7mm x 9.5mm or 66.5 total so I don't know where 80 mm^2 is coming from.

 

[function]

Anand must have measured Xenos incorrectly. With a ruler I measured the parent die of C1 to be 13.5mm x 13mm or 175.5 so their 182 figure is probably correct. The daughter die is 7mm x 9.5mm or 66.5 total so I don't know where 80 mm^2 is coming from.

Microsoft had changed the manufacturer of the daughter die by the time of Falcon (from NEC to TSMC I think). Maybe they actually started doing this before Falcon, or there was some combination of parts in different systems for some reason (repairs or refurbs maybe?).

Your 66.5 mm^2 for the daughter die is almost exactly the same as the 68 mm^2 they measured for the Falcon daughter die:

http://www.anandtech.com/show/2377/5

MS seemed to be happy with that daughter die right up until Valhalla.

 

[Quaz51]

28nm is ramping up just now, when was suppose to launch in Q4 2010 (TMSC).
For a fall 2013 console, a 20nm is out of question: too costly, and it won't have enough yields for launching a console. Same reason why CPU is going to be 32nm. IBM hasn't even used yet!

https://www.power.org/events/2010_ISSCC/Wire_Speed_Presentation_5.5_-_Final4.pdf

Looking at the die-shot, it's seems that almost half of space is used by accellerators and network.. with those out, at 32nm we would have a 160mm^2 chip, with 16 cores and 64 threads.

thanks
with 45nm:
AT node (4 cores + 2MB L2) = 42mm²
A2 core = 4mm²

 

[3dcgi]

Microsoft had changed the manufacturer of the daughter die by the time of Falcon (from NEC to TSMC I think). Maybe they actually started doing this before Falcon, or there was some combination of parts in different systems for some reason (repairs or refurbs maybe?).

Your 66.5 mm^2 for the daughter die is almost exactly the same as the 68 mm^2 they measured for the Falcon daughter die:

http://www.anandtech.com/show/2377/5

MS seemed to be happy with that daughter die right up until Valhalla.

I noticed that, but I'm pretty sure I was given this chip fairly early on and Xenos says A00 on it. It's not really important just figured I'd mention it for those that like to keep track of such things. If we assume Anandtech measured correctly then my version of the chip is different than any of the 3 they measured.

 

[AlNom]

Really wish those folks would take a photo with the ruler.

 

[Shifty Geezer]

Does no-one measure with a micrometer these days?

 

[liolio]

Dice gives its POV on next generation systems. Their part on multi chips (either CPU or GPU) sounds weird to me though.

 

[Proelite]

Dice gives its POV on next generation systems. Their part on multi chips (either CPU or GPU) sounds weird to me though.

Maybe one of the consoles is going to use power vr for their GPU? Would it make sense to have dozens of power vr 6 as a substitute for a single discrete GPU?

 

[AlNom]

What if it's twin GPGPUs and no "CPU".