Power7 probably doesn't make too much sense for them. As you say, they're best on the GPU side. I mean, aside from recent endeavours to shove as much graphics tasks to Cell, is there anything that really needs a massive CPU? (There is the mention of *ahem* physics in the GPU Architecture Job listing.) So... hey, here's an ultra-beefy GPU with unified shaders, lol-threads, textures, triangles, tessellation, etc.... Just throw things at it, it'll take care of the scheduling and threading and what-not.
i'm nerdixcited about more general purpouse gpu, but when i ask there's always the objection "you want to use every piece of silicon in the gpu only for graphic stuff because is this this that sell games"
nerdeluded
Cell (or more accurately SPUs) is in a class of its own at culling it beats a core i7 @2,6GHz badly (almost twice as fast) vs Xenon lose two three times faster and for the later I guess shading is not an option. Something that stroke me after watching dice presentation is that the Cell has actually 8 SPUs SOny decided to disabled one and relies on one SPU (and something) for security), I can only wonder what the figures would be if Dice ran their code on a full blown Cellmmm.... indeed. I do wonder how the current gen CPUs actually compare to more recent designs in the low power sector (Atom, Llano, ARM). Of course, even 45nm XCPU or Cell are still going to be an order of magnitude greater in power, but what if one scaled those particular designs up
mmm.... indeed. I do wonder how the current gen CPUs actually compare to more recent designs in the low power sector (Atom, Llano, ARM). Of course, even 45nm XCPU or Cell are still going to be an order of magnitude greater in power, but what if one scaled those particular designs up
lol
ಠ_ಠ
Well GDDR5 is boring but even on a 128bits bus it seem to offer enough bandwidth for the resolution next gen systems may be aimed at especially as deferred renderer are getting used more and more.
I wonder about it MS just swallowed the RD cost to implement xenos on SOI 45nm process. Move everything to bulk @ a process that won't give them much in regard to the number of dies per wafers seems like superflous expanse at this point. Moving Xenon+Xenos on GF 32nm process late in 2012 as well as edram to 40/45nm late in 2012 seems like a more likely scenario to me.
What got me exited is what Intel engineers working on Larrabee think of this and what they consider as design if they don't give up on the X86 ISA. They went in such lengths either on the software and hardware front, four way SMT, "Software multithreading", software rasterizer, super wide SIMD, etc.Hmm, are people more excited when cell is used for "general purpose", or graphics as in Dice presentations?
There's your answer
Does Intel need a counter to GPU computing?
So what was the point of investing in Larrabee? May they wanted to kill it while it is/was still a potential treat.
Hmm, are people more excited when cell is used for "general purpose", or graphics as in Dice presentations?
There's your answer
Vahalla is made on SOI 45 nm process if my memory serves right that's why I stated that they would have to reimplement everything on Bulk.
