PiNkY said:
I guess most of the dissension on this thread stems from interpreting "cell" as a physical implementation on the one hand and as a general concept for distributed computing on the other hand. The patent is bascially about a special way of organizing a memory controller, so I would not read too much into the accompanying use cases. Cell, as a concept, doesn't make too much economic sense if you just want to use it to power a video game console, it is a technology clearly geared towards distributed computing (thus the references to synchronisation by a global timestamp and the concept of generally thinking of programes as agents). Thus their main target will have to be servers (and eventually routers/switches). To come full circle, I d think that there will likely be some cell concepts in PS3 (hence all the talk about 90nm design methologies, which I would not expect for a 2007 high end processor as well as the references to first tape outs late last year), but the real cell chips for broadband distributed computing may well be 2007 releases. Also the idea of placing optical interconnects on a chip package seems to indicate broadband backbone usage more then a sub 500$/€ end user device.
The patent is quite a bit more than a description of a memory controller...
The patent defines the Processor Element or PE and the other bulding block of the architecture, the APU.
The patents described Cell as a scalable architecture that can fit small devices like a PDA and bigger devices like HDTVs, computers, etc...
The architecture described is geared for Distributed Computing, but it can do much more than that: in one way of looking at it this is also working in the field Jini was supposed to work in... devices connected over a network ( be it a LAN for example ) and inter-operating, discovering each other and communicate without running complex abstarction layers and having the user configure each device installing drivers and such.
I find this model fitting more ( edit: as you also pointed out ) a pervasive computing model ( easy inter-operation between several devices based on the Cell micro-architecture ) than disributed computing.
Sony's divisions reorganized around SCE a while and ago Ken Kutaragi raised in Sony's ranks in the recent past... clearly the PlayStation line is becoming more of a centerpiece to Sony strategy and can work effectively as Trojan horse for other technologies into the living room.
Cell can find implementations to fit a Sony Walkman, a PlayStation 3, a Sony DTV... when these devices are connected together they can talk and share data and you can use your PlayStation 3 as the effective media-center of the living room... PlayStation 3 doesn't need to have data processed by the toaster or the PDA, however doesn't have to distribute the processing...
( edit: sorry if the following paragraph seems redundant, but I put it also for other people who might be reading this here and there and might desire to have a longer post with less jumps here and there left to the reader's own research ).
Yes even if the architecture, Cell, would do it so well... having a common ISA shared by all devices that are implemented using this technology helps, as the patent says, to reduce the inefficiency caused by complex abstraction layers or Virtual Machines that convert this "universal" byte-code into the devices' machine code... Cell based devices would not need a Virtual Machine to do this "code translation".
An Apulet/Software Cell can migrate in order to be processed by another devices effectively sharing the load and this would make Cell a great architecture for clusters and render farm, but I cannot limit my vision to that.
Let's observe the patent ( edit: I just wanted to sort of give some more proofs to my argument... ):
[0003] The types of computers and computing devices connected to global networks, particularly the Internet, are extensive. In addition to personal computers (PCs) and servers, these computing devices include cellular telephones, mobile computers, personal digital assistants (PDAs), set top boxes, digital televisions and many others. The sharing of data and applications among this assortment of computers and computing devices presents substantial problems.
[0004] A number of techniques have been employed in an attempt to overcome these problems. These techniques include, among others, sophisticated interfaces and complicated programming techniques. These solutions often require substantial increases in processing power to implement. They also often result in a substantial increase in the time required to process applications and to transmit data over networks.
[0005] Data typically are transmitted over the Internet separately from the corresponding applications. This approach avoids the necessity of sending the application with each set of transmitted data corresponding to the application. While this approach minimizes the amount of bandwidth needed, it also often causes frustration among users. The correct application, or the most current application, for the transmitted data may not be available on the client's computer. This approach also requires the writing of a multiplicity of versions of each application for the multiplicity of different ISAs and instruction sets employed by the processors on the network.
[0006] The Java model attempts to solve this problem. This model employs a small application ("applet") complying with a strict security protocol. Applets are sent from a server computer over the network to be run by a client computer ("client"). To avoid having to send different versions of the same applet to clients employing different ISAs, all Java applets are run on a client's Java virtual machine. The Java virtual machine is software emulating a computer having a Java ISA and Java instruction set. This software, however, runs on the client's ISA and the client's instruction set. A version of the Java virtual machine is provided for each different ISA and instruction set of the clients. A multiplicity of different versions of each applet, therefore, is not required. Each client downloads only the correct Java virtual machine for its particular ISA and instruction set to run all Java applets.
[0007] Although providing a solution to the problem of having to write different versions of an application for each different ISA and instruction set, the Java processing model requires an additional layer of software on the client's computer. This additional layer of software significantly degrades a processor's processing speed. This decrease in speed is particularly significant for real-time, multimedia applications. A downloaded Java applet also may contain viruses, processing malfunctions, etc. These viruses and malfunctions can corrupt a client's database and cause other damage. Although a security protocol employed in the Java model attempts to overcome this problem by implementing a software "sandbox," i.e., a space in the client's memory beyond which the Java applet cannot write data, this software-driven security model is often insecure in its implementation and requires even more processing.
[0008] Real-time, multimedia, network applications are becoming increasingly important. These network applications require extremely fast processing speeds. Many thousands of megabits of data per second may be needed in the future for such applications. The current architecture of networks, and particularly that of the Internet, and the programming model presently embodied in, e.g., the Java model, make reaching such processing speeds extremely difficult.
[0009] Therefore, a new computer architecture, a new architecture for computer networks and a new programming model are required. This new architecture and programming model should overcome the problems of sharing data and applications among the various members of a network without imposing added computational burdens. This new computer architecture and programming model also should overcome the security problems inherent in sharing applications and data among the members of a network.
[0057] The computers and computing devices connected to network 104 (the network's "members") include, e.g., client computers 106, server computers 108, personal digital assistants (PDAs) 110, digital television (DTV) 112 and other wired or wireless computers and computing devices. The processors employed by the members of network 104 are constructed from the same common computing module. These processors also preferably all have the same ISA and perform processing in accordance with the same instruction set. The number of modules included within any particular processor depends upon the processing power required by that processor.
You notice how Phiber Optic links are present in some diagarams of the patent and I have seen those diagrams and their description too, but IMHO they mention fiber optic links as possible extra features to add to the processors as a possible solution for implementations like servers that need extremely high external bandwidth with other computers ( again, like in a big render-farm ).
Not all Cell chips need fiber optic PHYs on the chip... as you said backbone routers might need to do that... Toshiba more than Sony would be interested in this aspect as they wanted to use the Emotion Engine for routers as well...
There are other technologies mentioned in that patent, but I do not think we can safely use them to deduce which market the chip is going to cover ( as the patent says, this architecture is intended for all markets afterall ).
Let me just make a small example:
[0063] PE 201 can be constructed using various methods for implementing digital logic. PE 201 preferably is constructed, however, as a single integrated circuit employing a complementary metal oxide semiconductor (CMOS) on a silicon substrate. Alternative materials for substrates include gallium arsinide, gallium aluminum arsinide and other so-called III-B compounds employing a wide variety of dopants. PE 201 also could be implemented using superconducting material, e.g., rapid single-flux-quantum (RSFQ) logic.
In the last paragraph the patent mention a possible physical implementation of the Broadband Engine chip and neither in this case as it was for the Optical Interfaces comment we should deduce that this architecture is geared for a specific market, like for supercomputers because it can be implemented using RSFQ logic.
IMHO, this architecture is designed purposely to be modular and to scale so that it could be used for several devices ranging from a PDA to a Server ( edit: again a small summary for people who are just glancing these last posts and do not want to read all 10 pages... ).
[0073] FIG. 7 illustrates a chip]/u] package for a BE 702 with two optical interfaces 704 and 706 for providing ultra high speed communications to the other members of network 104 (or other chip packages locally connected). BE 702 can function as, e.g., a server on network 104.
The Broadband Engine chip could be implemented with two optical interfaces for fiber optic connections and it also says where this special chip could be used in, a server for example.
They describe the situations where optical interfaces would be needed and how these optical interfaces could be implemented, but IMHO they do not make a case for the Cell micro-architecture to be relegated to Server space.
[0077] FIG. 11A illustrates the integration of optical interfaces into a chip package of a processor of network 104. These optical interfaces convert optical signals to electrical signals and electrical signals to optical signals and can be constructed from a variety of materials including, e.g., gallium arsinide, aluminum gallium arsinide, germanium and other elements or compounds. As shown in this figure, optical interfaces 1104 and 1106 are fabricated on the chip package of BE 1102. BE bus 1108 provides communication among the PEs of BE 1102, namely, PE 1110, PE 1112, PE 1114, PE 1116, and these optical interfaces. Optical interface 1104 includes two ports, namely, port 1118 and port 1120, and optical interface 1106 also includes two ports, namely, port 1122 and port 1124. Ports 1118, 1120, 1122 and 1124 are connected to, respectively, optical wave guides 1126, 1128, 1130 and 1132. Optical signals are transmitted to and from BE 1102 through these optical wave guides via the ports of optical interfaces 1104 and 1106.
[0078] plurality of BEs can be connected together in various configurations using such optical wave guides and the four optical ports of each BE. For example, as shown in FIG. 11B, two or more BEs, e.g., BE 1152, BE 1154 and BE 1156, can be connected serially through such optical ports. In this example, optical interface 1166 of BE 1152 is connected through its optical ports to the optical ports of optical interface 1160 of BE 1154. In a similar manner, the optical ports of optical interface 1162 on BE 1154 are connected to the optical ports of optical interface 1164 of BE 1156.
Earlier it shows diagrams of the Broadband Engine without any optical interface and having a connection to an I/O ASIC which is connected to external memory ( Rambus Yellowstone can nicely provide ~25.6 GB/s of bandwidth with a 64 bits memory controller, a 400 MHz base clock and 3.2 GHz signalling rate... ok I digressed, sorry 
)...
Sony is investing lots of money into this architecture and understandably they want it to fit it in as many products as they can...
In the article it mentions that, even if IBM was allowed to take the HW designing lead, Sony and Toshiba engineers were deeply involved in the process and top execs from both Sony and Toshiba were present... it also mentions how Sony and Toshiba engineers were important as they provided the knowledge of what it takes to make succesful embedded products and the requirements of microarchitectures designed for consumer electronic devices...
Another issue I have is that I do not think Sony is, in parallel, designed an uber-powerful architecture for Playstation 3 that is totally unrelated to Cell... especially considerign that the development of Phase 1-3 workstatiions was halted and so was the GScube project...
BTW, Toshiba is building a new plant in Japan and Sony will invest into it... the plant will cost $2+ billion and it was mentioned in the PR Cell manufacturing...
I do see Cell as being more important to Sony than what some people think.
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