Next-Gen iPhone & iPhone Nano Speculation

[Mariner]

Here's a video from a Russian site, purportedly showing the new iP6:

http://www.gsmarena.com/apple_iphone_6_gets_disassembled_before_its_official_debut-news-9516.php

Looks a bit too elaborate to be a hoax! I think the 4.7" screen is a good size and the device is only slightly larger than the iP5s. Ought to sell very well, and if Apple really are pushing out NFC payments that can only be a good thing (providing it isn't Apple-only!). I understand they've had NFC payments using phones in some Asian countries for years so it's about time the rest of us caught up and had this option!

 

[Lazy8s]

The evolution of the market has made the title of this thread amusingly outdated.

Analysts were way off with their perception that the original 3.5" display was too large to be truly mass market and that a smaller size like on the Palm Pre was needed.

 

[Lazy8s]

Apple's reasoning may have been related to power consumption for the low amount of RAM, and, in turn, a smaller battery capacity allowing for a more compact form factor, but the trade off wasn't justified even in this past generation. Getting left even further behind in this specific spec for this year would lead to a lot of frustration.

As for the areas of SoC design that Apple will use to push the A8's performance, I'm expecting them to rely more than usual on clock speed this generation. 20 nm, while mostly a boost to density, will help a little, and their CPU design teams, having come off the launch of new architectures in each of the last two years, will probably be focused more on tuning their pipeline for speed than redefining it again so soon.

At a minimum, I could see a 600/633 MHz G6630 put with a 1800/1900 MHz dual core Cyclone v2 and an upgrade to the on-die SRAM.

 

[Arun]

Qualcomm baseband looks to be MDM9625M so it's 28nm.
A8 package is slightly smaller but that doesn't tell us much about die size unless we can tell what the ball pitch is?

 

[anexanhume]

Qualcomm baseband looks to be MDM9625M so it's 28nm.
A8 package is slightly smaller but that doesn't tell us much about die size unless we can tell what the ball pitch is?

The baseband is 9625. I confirmed the presence of WTR1625L on the back.

None of the pictures have good enough resolution to tell the ball pitch, but it does seem pin count has gone down.

 

[Deleted member 13524]

I don't understand.
Was there some bug in the forum or did someone actually erase my post about possible implications that could affect the iphone 6's launch due to the latest news about iCloud?

 

[Gubbi]

I don't understand.
Was there some bug in the forum or did someone actually erase my post about possible implications that could affect the iphone 6's launch due to the latest news about iCloud?

I read it, so it was posted correctly.

Cheers

 

[Rys]

I deleted it because it's not going to affect the launch, and it's noise (it's not confirmed in any way that it was an iCloud breach that caused the leaked photographs).

 

[Arun]

None of the pictures have good enough resolution to tell the ball pitch, but it does seem pin count has gone down.

1155 pins for A8 vs 1292 pins for A7 (-10% or so). That could mean a smaller die size but it's not such a big reduction that it couldn't be explained by other factors TBH.

 

[Deleted member 13524]

1155 pins for A8 vs 1292 pins for A7 (-10% or so). That could mean a smaller die size but it's not such a big reduction that it couldn't be explained by other factors TBH.

Could this mean we're not to expect quad-channel 32bit or dual-channel 64bit RAM?

Or could they have put more peripherals inside the SoC?

 

[anexanhume]

1155 pins for A8 vs 1292 pins for A7 (-10% or so). That could mean a smaller die size but it's not such a big reduction that it couldn't be explained by other factors TBH.

Yes. I am looking forward to seeing the die annotated to see if they moved any functionality onto the die that allowed them to reduce the I/O.

Could this mean we're not to expect quad-channel 32bit or dual-channel 64bit RAM?

Or could they have put more peripherals inside the SoC?

Hynix sent an updated part decoder to macrumors that confirmed it is 8Gb, x32, 2 channel. It basically confirms the A7 and A8 memory are identical outside of die size and number of balls.

(following this link will trigger a PDF download) http://forums.macrumors.com/attachment.php?attachmentid=488196&d=1409580456

 

[Helmore]

Honest question, how many pins, roughly, are usually for power delivery? Probably depends on maximum power draw, but at a guess? I don't even mean for Apple's SoCs specifically.

 

[Grall]

On PC processors, the majority are power/ground, I believe, to ensure uniform voltage/current delivery across the die. I/O pins tend to be the outermost rows around the edge of the die, although there may be exceptions to this rule, what do I know.

For mobile chips which are inherently very low power, the proportion of I/O to power/gnd might be higher...or so logic would dictate anyway, I would think. Phone SoCs have lots of peripheral hardware in them, so lots of I/O - LCD and touch screen data links, USB, multiple sensors, multiple radio transcievers, audio codec, cameras, GPIO for buttons and connector sensing and whatnot, and so on.

 

[anexanhume]

On PC processors, the majority are power/ground, I believe, to ensure uniform voltage/current delivery across the die. I/O pins tend to be the outermost rows around the edge of the die, although there may be exceptions to this rule, what do I know.

For mobile chips which are inherently very low power, the proportion of I/O to power/gnd might be higher...or so logic would dictate anyway, I would think. Phone SoCs have lots of peripheral hardware in them, so lots of I/O - LCD and touch screen data links, USB, multiple sensors, multiple radio transcievers, audio codec, cameras, GPIO for buttons and connector sensing and whatnot, and so on.

Yup. PC processors are starting to get regulators inside them too, which means they can tolerate a little more IR drop variability. For A8, I think it's likely safe to assume that the die power density and per pin current numbers stayed fairly consistent. So unless they drastically reduced I/O, they probably dropped some power pins with the shrink.

 

[Arun]

So unless they drastically reduced I/O, they probably dropped some power pins with the shrink.

I'm still not sure why I should believe it's TSMC 20nm when it doesn't match TSMC's production timeframe (volume shipments started in June which feels awfully late for millions of devices shipping in September...)

 

[anexanhume]

I'm still not sure why I should believe it's TSMC 20nm when it doesn't match TSMC's production timeframe (volume shipments started in June which feels awfully late for millions of devices shipping in September...)

I understand your skepticism given TSMC's reputation on process ramp up . Supposedly, TSMC sent hundreds of engineers to Apple last year for their collaboration on the project.

http://online.wsj.com/articles/tsmc-starts-shipping-microprocessors-to-apple-1404991514

(paste in google for full article)

 

[Arun]

I understand your skepticism given TSMC's reputation on process ramp up

Well, TSMC did an amazing job at 28nm and completely obliterated their foundry competitors on both volume and yields. It's always extremely risky to bet your entire end-product roadmap on a new chip technology though! Let's say it didn't work out; what would Apple do, delay the iPhone by 6 months, or release a new iPhone with the same A7 chip? Neither are very appealing options to say the least...

Supposedly, TSMC sent hundreds of engineers to Apple last year for their collaboration on the project.

I have no idea if that's true, but I'm not arguing whether or not Apple might or might not use TSMC in the future, only that it makes little sense for a phone in September because of this:

After two years of meticulous preparation, we began volume shipments of our 20 nanometer wafers in June. The steepness of our 20 nanometer ramp sets a record. We expect 20 nanometer to generate about 10% of our wafer revenue in the third quarter and more than 20% of our wafer revenue in the fourth quarter and we expect the demand for 20 nanometer will remain strong and will continue to contribute more than 20% of our wafer revenue in 2015.

[...]

We'll talk about the 20 nanometer impact first. In the second quarter, we have very, very small shipments, but we have incurred some cost already. So the impact to margin is about 1% to your point, okay, that's for 20 nanometer.

While that does indicate a VERY fast ramp, I don't see how that works for a September launch given the lead-time and the fact TSMC barely shipped any ships before July. It's not strictly impossible but it seems way too aggressive and way too likely to lead to supply issues even with decent yields.

 

[anexanhume]

When would you expect shipment to have started? Supposedly, production started late February: http://translate.google.com/transla...firefox&hs=QRy&rls=org.mozilla:en-US:official

 

[Entropy]

I have no idea if that's true, but I'm not arguing whether or not Apple might or might not use TSMC in the future, only that it makes little sense for a phone in September because of this:
While that does indicate a VERY fast ramp, I don't see how that works for a September launch given the lead-time and the fact TSMC barely shipped any ships before July. It's not strictly impossible but it seems way too aggressive and way too likely to lead to supply issues even with decent yields.

You shifted a month from June to July there.
They were in full production swing in April, did their initial volume shipments in June - and we still don't know when the iPhone6 will be available to consumers. But Apple will have had a three month lead of volume chip shipments to work with before the launch. That said, I wouldn't be surprised to see shortages of stock until after Christmas 2014.

 

[Grall]

There's always shortages of stock with new iphones. This goes without saying, pretty much.