IMG confirm that Intel is using SGX

Reading the Anandtech article. Thats a high number of chips to get this working. Even more if the phone has an above 5mp camera.
 
Reading the Anandtech article. Thats a high number of chips to get this working. Even more if the phone has an above 5mp camera.
That's my main problem with it too. 3-5 chips instead of 1-2 with ARM SoCs. Hopefully with Medfield this problem will be resolved. H2/2011 could get interesting.

Regarding SGX, I'm a little bit disappointed that Intel didn't choose SGX545 over SGX535. I really thought Intel bould be the SGX545 launch partner.

And finally someone used IMG's VXE core in a SoC (well, compared to ARM SoCs Intel's Z600 doesn't really qualify as a SoC).
 
I'm curious to see if a dual core A9 would be competitive on perf/W, maybe it's me but isn't easy to imagine all that stuff closed on a phone and lasting enought...

And what about "we don't support WP7"?
WP7 it's built for arm processors, what kind of support is intel talking?
 
And what about "we don't support WP7"?
More like MS kicked them out the door (for whatever reasons), and with the benefit of hindsight they figure that grapes are sour.

WP7 it's built for arm processors, what kind of support is intel talking?

I guess MS refused to maintain 2 ISA branches just to focus better on what they have now.
 
Reading the Anandtech article. Thats a high number of chips to get this working. Even more if the phone has an above 5mp camera.

anyone putting a >5 mp camera in a cellphone with no optics or bad plastic optics should be shot. Hell, realistically, I haven't seen a cellphone except the specific cameras with a built in cell phone, that even has optics worthy of 1 MP.
 
More like MS kicked them out the door (for whatever reasons), and with the benefit of hindsight they figure that grapes are sour.

I guess MS refused to maintain 2 ISA branches just to focus better on what they have now.

yes i know, but anand isn't a stupid, would have make joke of this statement if it was completely pr stunt
maybe has something to do with arm emulation over x86? looks fairly impossible btw...
 
Don't know about the optics but Nokia's N8 at least there's suppose to be a big size sensor in there.

and from the video and photo made with it, its worth it

this first intel generation with limited "phoneness" looks like an advanced research project partially offloaded to the buyers' pockets
 
Dual-core A9 SoCs launching around Moorestown's release leave it at a competitive disadvantage in many ways, but Medfield takes advantage of Intel's lead in process technology to really shine.

Just because IMG needs to cite a specific clock speed as a point of reference for quoting SGX performance and that point they chose was 200 MHz, it doesn't mean their cores have been running at 200 MHz in the actual phones all this time. Articles always seem to assume this. They also always assume that the performance difference between SGX535 and the 530 is double the triangle rate and not double the texel fill.
 
Don't know about the optics but Nokia's N8 at least there's suppose to be a big size sensor in there.

I'm not sure but I'd guess the N8 contains a Broadcom SoC (at least I can't think of any other SoC with an ARM11). Yes it contains a OGL_ES2.0 GPU in its paperspecs with funky peak triangle rates but I'm afraid that's about it.

That's my main problem with it too. 3-5 chips instead of 1-2 with ARM SoCs. Hopefully with Medfield this problem will be resolved. H2/2011 could get interesting.

Regarding SGX, I'm a little bit disappointed that Intel didn't choose SGX545 over SGX535. I really thought Intel bould be the SGX545 launch partner.

And finally someone used IMG's VXE core in a SoC (well, compared to ARM SoCs Intel's Z600 doesn't really qualify as a SoC).

I'm personally not disappointed at all. SGX545 might have a high feature-set but it also doesn't come for free either. I'd rather prefer Intel to invest for it's next generation of embedded SoCs that die area in performance or else in SGX543 MP. According to IMG under 65LP (@200MHz) 545 equals 12.5mm2 and 543 8mm2 per core. 543 might be limited to SM3.0+ but with a 2MP/16mm2@65LP you get more than twice the performance of a 545.

For the moment and always IMHO fill-rates have a sizable importance in the embedded space. Going to a 545@200MHz vs. 535@400MHz as an example means twice the fill-rate in the latter case, since all cores =/>535 have 2 TMUs. Frequency doesn't scale unfortunately in parallel with die area.
 
yes i know, but anand isn't a stupid, would have make joke of this statement if it was completely pr stunt
maybe has something to do with arm emulation over x86? looks fairly impossible btw...
May be he didn't want to offend his contacts @Intel? :???:
 
Apart from the DRAM I don't see how the extra chips matter, tiny chips with tiny bandwidth interfaces ... their integration wouldn't save much power or area AFAICS.
 
I'm personally not disappointed at all. SGX545 might have a high feature-set but it also doesn't come for free either. I'd rather prefer Intel to invest for it's next generation of embedded SoCs that die area in performance or else in SGX543 MP. According to IMG under 65LP (@200MHz) 545 equals 12.5mm2 and 543 8mm2 per core. 543 might be limited to SM3.0+ but with a 2MP/16mm2@65LP you get more than twice the performance of a 545.

For the moment and always IMHO fill-rates have a sizable importance in the embedded space. Going to a 545@200MHz vs. 535@400MHz as an example means twice the fill-rate in the latter case, since all cores =/>535 have 2 TMUs. Frequency doesn't scale unfortunately in parallel with die area.

Tunnel Creek is using SGX535 @ 200Mhz-400Mhz.
Sodaville (CE4100) is using SGX545 @200-400Mhz.

Today we get that Moorestown is similarly using SGX535 @ 200-400Mhz.

So the pattern is getting clear, what Intel use on one Soc platform, they use on the others.

Intel said at IDF that the generation after tunnel creek would be x5 the graphics performance of tunnel creek. The said today that Medfield would be x2 the graphics of Moorestown.

Assuming they stick with IMG, clearly looks like will be seeing either 545 or 543MP next year in Medfield, with a higher clocked/increase cores version in Tunnel Creeks successor.
 
Apart from the DRAM I don't see how the extra chips matter, tiny chips with tiny bandwidth interfaces ... their integration wouldn't save much power or area AFAICS.
What do you mean with tiny chips? Apart from the extra DRAM chip, there's also Langwell, which is even bigger than Lincroft (14x14x1.3mm vs. 13.8x13.8x1.1mm).
Thank god at least Langwell is gone for sure with Medfield next year (i really hope the extra DRAM chip is gone too).
IntelAtomProcessorZ6xx(Lincroft)and_PlatformControllerHub_package2_sm.jpg


For tablets this isn't that big of a problem, but the main target here is smartphones.
I think 2-3 chips more matter if you want to build compact smartphones with mainboards like this (especially for next-gen devices that launch in Q4/2010):
500x_open19_01.jpg
 
Arun, if you're reading, do you have any preliminary thoughts on Z600 and the silicon required for designs, specifically with regards to integration and the area and number of chips (especially the mixed signal chip and what radio ICs you see being paired with the chipset) ?
 
Mike11 ... okay, but those were already known about ... I just think making a big deal being made about the extra power and RF chips seems overblown.
 
For tablets this isn't that big of a problem, but the main target here is smartphones.
I think 2-3 chips more matter if you want to build compact smartphones with mainboards like this (especially for next-gen devices that launch in Q4/2010):

The platform doesn't totally seem to exclude iphone sized devices, given that Anandtech stated that the demo phone from AVA was narrower, thinner, but a bit longer than the iphone 3GS, and included a 1500mAh battery
 
Arun, if you're reading, do you have any preliminary thoughts on Z600 and the silicon required for designs, specifically with regards to integration and the area and number of chips (especially the mixed signal chip and what radio ICs you see being paired with the chipset) ?
Oh hai!

The level of integration is just fine besides for the very real disadvantages of the two-chip approach and the lack of Package-on-Package DRAM for LPDDR1 (a very strange omission since it's widely supported on 14x14 packages - surely Intel didn't *need* to use a 13.8x13.8 package?). One interesting point is that both packages are 0.5mm pitch, versus 0.4mm for high-end ARM SoCs, which could save a little bit of cost on the PCB but besides that it's apparent that Intel's packaging expertise is rather below average.

The I/O partitioning between the two chips is also bizarre: LVDS on Lincroft and HDMI on Langwell, for example - whereas ARM competitors usually integrate HDMI but need a separate chip for LVDS in tablet designs (because LVDS normally needs extra process steps on modern process nodes iirc). Putting the ISP on Langwell is also a bizarre choice and feels more like a late-stage addition (same for HDMI), although in the end it doesn't really matter. On the other hand being limited to 5MP is rather absurd, especially as it's easy to get an on-sensor-package ISP at 5MP or below (see: Apple, they don't integrate an ISP!) but rare above so you'd need a moderately expensive discrete chip.

In the seemingly cancelled LG GW990, the Z600 was combined with a Ericsson 3G module (i.e. pre-certified in several key ways to simplify design/time-to-market but increasing costs) based, afaik, on the ST-Ericsson M340. But it could probably be combined with any of the very popular slim modems in the industry, such as the Infineon X-Gold 616 or Icera ICE8040 for WCDMA and Qualcomm QSC6085 for CDMA. The area penalty of not integrating the baseband is diminishing all the time, and the RF side is probably more important right now anyway (see: Infineon UE2 for a leading-edge example). The decision to work with Nokia on baseband technology for the mid-term highlights Intel's lack of understanding of the field, IMO, and is a negative overall in my mind.

Power management is interesting. The various implementations of Briertown by different analogue companies (not necessarily single-chip in fact but that's not important) are probably the most advanced chips in their field I'm aware of - and also the most expensive. Seriously, NINE DC/DC?! The latest ARM SoCs used 4 at most. Part of it is the extra complexity of the two-chip approach each needing different voltages, but there's also a nice bonus feature: you can power the baseband with no secondary power management chip. It's really a system solution (using partnerships with the likes of ST-Ericsson and Icera) which is nice, even if overall power management is still more expensive and it limits their choices a bit because Infineon for example integrates the PMU (SoC on 65nm, interestingly back to SiP on 40nm - guess they figured the cost/mm2 was too expensive for something that nearly doesn't scale!)

Connectivity-wise, WLCSP and QFN packages are very cheap, and there isn't that much that could be shared between standards anyway. So the lack of integration is irrelevant. The only company that pushed aggressively on that front in the 3G market was Broadcom, and they achieved a grand total of zero design wins for their 'Zeus' baseband (see Linley Group's news on that). Integration is nice, but it's nearly always secondary to other things.

Talking of other things:I could be reading the slides wrong, but it seems to me they're hinting at only 720p support when limited to 32-bit LPDDR1. Being limited to 20Mbps at 1080p is also intriguing, I wonder if this is the same VXD375 as in the A4? The advantage there against TI or NVIDIA or basically nil to be honest (NV is limited to low bitrates at HP on 1080p, but it's enough for YouTube support iirc). At least in terms of 3D graphics, it's truly leading-edge with such a highly clocked SGX535. The idea of putting an audio island on Langwell also seems like a fine strategy even if power consumption there is still a fair bit higher than you'd want it to be.

Overall it's obviously a MASSIVE step-up from Menlow, and Medfield should be truly excellent in many ways. I wonder how Rayfield would react if he realized I was actually (only slightly) too *pessimistic* about Moorestown's power numbers, hah. However, it remains expensive and, most importantly, the game has moved on. When Menlow came out the OS war was still raging and this coupled with Moblin and a 3D UI could have been a very strong contender. But now they're pushing for MeeGo and Android (presumably Chrome OS later) - but Android doesn't make perfect sense. The Java apps will be compatible cross-ISA, but as of 1.5 (or was it 1.6?) there's a native SDK which compiles directly to ARM, and it's what's used for anything interesting 3D-wise for example. So x86 has now become a disadvantage OS-wise (even if not as much as it could have been) which is ironic given Intel's past marketing.

The biggest business opportunity for Intel here is if they can get Nokia completely on board in larger MeeGo form-factors (5-12"), along with a bunch of ODMs and PC-centric OEMs (even though they all have ARM, usually Tegra, R&D programs now). They won't get smartphone volume on this part, no way, but a few flagship design wins could give them credibility with Medfield, and that would spice things up.

Intel's 32nm process seems very strong, and the competitiveness of ARM-based SoCs will depend a bit on TSMC's execution for 28nm - specifically the 28LPT and 28HPM nodes (I don't know about TI, but I know nearly for certain that those are the specific process variants used by both NVIDIA & Qualcomm for Tegra/Snapdragon 3 & 4 respectively). Moorestown feels to be a bit too little, a bit too late to me - but definitely big kudos to the engineering teams either way.
 
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