Yes ive read a swedish article on Zen3, it's a crazy IPC improvement over Zen2. Totally outperforms anything Intel has on offer. We got a beastly improvement for GPUs, one of the biggest leaps ever, but the CPU side is showing some nice things too now with Zen3. Wonder if intel can counter this, dont think so.
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Yes ive read a swedish article on Zen3, it's a crazy IPC improvement over Zen2. Totally outperforms anything Intel has on offer. We got a beastly improvement for GPUs, one of the biggest leaps ever, but the CPU side is showing some nice things too now with Zen3. Wonder if intel can counter this, dont think so.
hoom
Veteran
But is it at stock speeds/reasonably attainable OC? And if its stock can it OC similar amounts to Intel (I actually lost track on if the current Intel stuff actually OCs much)
Beating stock Intel wouldn't be much use if Intel still have easy big OC like on my 6600K & the AMD chips are basically maxed out.
Leoneazzurro5
Regular
In any case, AMD is highlighting gaming performance in their Zen3 presentation:
https://www.amd.com/en/events/gaming-2020#.X3Z8AiHjtLg.twitter
They seem quite proud of their product, it must be seen, what actual tests will say.
https://www.amd.com/en/events/gaming-2020#.X3Z8AiHjtLg.twitter
They seem quite proud of their product, it must be seen, what actual tests will say.
hoom
Veteran
Oh announcement is 8th = next week, somehow I'd got in my mind its 13th.
Saw rumors of launch maybe by 20th.
Exciting times
Dang, may have jumped the gun on buying new bits for rebuilding my Dads PC during recent sale, 2 weekends later & still haven't even put it together, bound to be some big price drops once Zen3 comes online.
Oh well, quad core Zen2 with an M2 SSD & 16GB RAM is still gonna be a massive upgrade from his 2core + HT i3 with spinny drive & mobo incapable of handling more than 4GB RAM.
Saw rumors of launch maybe by 20th.
Exciting times
Dang, may have jumped the gun on buying new bits for rebuilding my Dads PC during recent sale, 2 weekends later & still haven't even put it together, bound to be some big price drops once Zen3 comes online.
Oh well, quad core Zen2 with an M2 SSD & 16GB RAM is still gonna be a massive upgrade from his 2core + HT i3 with spinny drive & mobo incapable of handling more than 4GB RAM.
D
Deleted member 7537
Guest
Oh announcement is 8th = next week, somehow I'd got in my mind its 13th.
Saw rumors of launch maybe by 20th.
Exciting times
Dang, may have jumped the gun on buying new bits for rebuilding my Dads PC during recent sale, 2 weekends later & still haven't even put it together, bound to be some big price drops once Zen3 comes online.
Oh well, quad core Zen2 with an M2 SSD & 16GB RAM is still gonna be a massive upgrade from his 2core + HT i3 with spinny drive & mobo incapable of handling more than 4GB RAM.
I’m already putting my whole system for sale on ebay, including the monitor. I will upgrade to 1440p 144hz.
I will only keep the 2060 until the 3070 becomes widely available.
That's for sure will turn out great when one will wish 5700 for Christmas.
D
Deleted member 13524
Guest
They'd need to use the xx50 or xx70 suffix to close the loop. Maybe we'll get lucky with the mobile APUs.
Anyone got any thoughts or guesses on how they will be handling the move from 2 cores sharing the L3 to 4 cores?
As I understand it, currently they cores just use bank and way sharing to access the L3, but i dont think that will scale well for 4 cores sharing a single L3.
A simple crossbar would probably work if it's only needs to serve 4 cores?
Perhaps a small ring bus, or dual rings, between each of the cores and the L3 might be the result?
Or does the IF get extended to the Core <-> L3 interface aswell? which might bring some intelligence to the system, and assist in cache misses?
4 Core CCX's seems to be the sweet spot, so i suspect that will remain.
I'm interested to see if they introduce a new IO die?
- perhaps a shrink to 7nm which would save a bit of power
- improved memory controller + maybe support for higher DDR speeds ( in client system anyway)
- maybe a faster / new version of IF between IO die and chiplets
I'm not sure what they can do for quick and easy gains inside the actual cpu core itself.
more OOB buffers, maybe larger trace cache?
i doubt we will see anything radical like more execution units or a new front-end / decoders.
I also think the L1and L2 sizes are likely fixed though.
gaining a cycle lower latency on the L2 might be possible?
anyway it's all crazy speculation for the next 24 hours or so!
As I understand it, currently they cores just use bank and way sharing to access the L3, but i dont think that will scale well for 4 cores sharing a single L3.
A simple crossbar would probably work if it's only needs to serve 4 cores?
Perhaps a small ring bus, or dual rings, between each of the cores and the L3 might be the result?
Or does the IF get extended to the Core <-> L3 interface aswell? which might bring some intelligence to the system, and assist in cache misses?
4 Core CCX's seems to be the sweet spot, so i suspect that will remain.
I'm interested to see if they introduce a new IO die?
- perhaps a shrink to 7nm which would save a bit of power
- improved memory controller + maybe support for higher DDR speeds ( in client system anyway)
- maybe a faster / new version of IF between IO die and chiplets
I'm not sure what they can do for quick and easy gains inside the actual cpu core itself.
more OOB buffers, maybe larger trace cache?
i doubt we will see anything radical like more execution units or a new front-end / decoders.
I also think the L1and L2 sizes are likely fixed though.
gaining a cycle lower latency on the L2 might be possible?
anyway it's all crazy speculation for the next 24 hours or so!
hoom
Veteran
Livestream in ~10hrs
Supposedly also big architecture IPC improvements which I think implies more execution units not just cache/decoders etc.
But who knows, could be nearly anything given lack of rumor :neutral:
Zen2 has 4* cores per 16MB L3, the only apparently reliable info we have on Zen3 is its going to 8* cores per 32MB L3.
Supposedly also big architecture IPC improvements which I think implies more execution units not just cache/decoders etc.
But who knows, could be nearly anything given lack of rumor :neutral:
Seems like you got some things mixed up there.
CCX is defined by shared L3, current CCXs are 4 cores because 4 cores (not 2 like you suggested) share same L3 slice.
In Zen 3, this will change so 8 cores share the same L3, which means CCX (if they still want to use that term) will be 8 cores.
People have already answered about the L3 and CCXs but to your other points:-
-IO die is likely to be the same or a newer revision/stepping. They aren't introducing any new IO features or socket so there isn't really any need for a new IO die. Using the existing die would also save cost and engineering resources. I wouldn't be surprised if the focus has been more on Zen 4 over the last 12 months as that is introducing some major changes, particularly on the server side (DDR5, PCIE5, CXL, etc). And 7nm is going to be reserved for CPUs/GPUs only at this point. Rumour is that there will be a new 6nm IO die with Zen 4, as CPUs will be moving to 5nm. Also possible that it could be 12LP+ die from Globalfoundries as they still have a WSA to fulfill. That could work fine for consumer IOD and the 6nm would be a better fit for servers.
-DDR4 speeds are likely to remain at JEDEC 3200 specs officially, though overclocking beyond 4 Ghz was possible anyway. FCLK OC could increase, hopefully 4 GHz be possible. If the IO die is the same then perhaps there wont be much change.
-IF is also likely to remain the same due to socket and compatibility reasons. New version of IF is expected with Zen 4.
I agree with your points on the cache sizes remaining the same and also expect one cycle lower latency on L2. Decoders and front end could be beefed up.
Almost there! We should know in about 6 hours!
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D
Deleted member 7537
Guest
Yay AMD is going to finally beat ST Skylake performance.
Yay AMD is going to finally beat ST Skylake performance.
Fixed quote for you mate
Zen 1 had higher IPC than Skylake in many areas, but memory latency sensitive algorithms were better off on Skylake CPU's.
D
Deleted member 13524
Guest
Is it only CPUs or should we expect APU talk as well?
It's obvious that they will be talking about Vermeer, but if they're also talking about Cezanne (Zen3 + Vega) then we might get to know what Vang Ghogh is all about (Zen2 + RDNA2 + LPDDR5).
It's obvious that they will be talking about Vermeer, but if they're also talking about Cezanne (Zen3 + Vega) then we might get to know what Vang Ghogh is all about (Zen2 + RDNA2 + LPDDR5).
Too early for Cezanne I think, that'll be CES stuff more likely, same for Van Gogh. But the bigger question is IMO whether Van Gogh is even coming to laptops etc in general, or could it be something like custom made for Microsoft Surface or something?Is it only CPUs or should we expect APU talk as well?
It's obvious that they will be talking about Vermeer, but if they're also talking about Cezanne (Zen3 + Vega) then we might get to know what Vang Ghogh is all about (Zen2 + RDNA2 + LPDDR5).
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