I don't think he realized that the top area are actually vertical sliders.
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AMD: Speculation, Rumors, and Discussion (Archive)
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I don't think he realized that the top area are actually vertical sliders.
Effectively.. if you dont know the actual crimson driver, you can imagine it is just a graphic representation.
Ah.. I realized that they were vertical sliders, but I was interpreting the controls as a graph, with fixed frequencies on the X axis and vertical sliders to set voltages for those frequencies on the Y axis. Using vertical sliders to set horizontal X coordinates is a GUI design fail, but a harmless one. Thanks for making me look at the design again.
Edit: Looking more, I still don't understand the GUI. Maybe there's a mode with the small round white buttons on the left to switch between setting frequency setting and voltage setting? And the graphs are then not frequency vs voltage at all, but "state number" vs voltage.
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Well effectively, the Crimson drivers could been a bit derouting at first.. ( the box only represent the clock set and change ofc when you move the sliders ). Well, its offtly the case when things change, but prettty logical now that they have nearly finish to put all the settings there. ( still some specific monitors one are missing yet and open the old Catalyst control center )
That's a 15% increase... for something something V^2 power.
Talking about HPC from an FP64/double precision operation perspective, what will be AMD's strategy?
I assume their priority would be to compete in Deep Learning/Training/data processing/analytics by using 'Big Vega' also in the Pro range; but will they improve the S9170 with the 14nm node and architecture improvements or concede that market (requiring double precision operations) in the longer term.
From price/FP64 performance the Nvidia PCIe P100 works out cheaper and with better performance, saving grace for the S9170 is that the PCIe P100 card has a Q4 general availability.
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Well im a bit worry about this.. On the past, if it was not directly allowed by the standard driver overclocking tool, this was for dont have trouble with peoples killing their hardware too easely. Now, theres a lot of protection on hardware against abnormal execution who could limit the damage.. or even just bugs on displaying.
( i have kill many 9700pro in the past by trying push the limit on OC, they was no protection at alll, and in general when benching, your monitor was suddenlly display geometric figure instead of the " normal image"; this was mean, your gpu is dead ).
This said, i can imagine, if they alllow it, the reason is the risk is controlled. But we completely at the invert side of the Greenlight system of nvidia.
I
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Well the Q4 P100 PCie version, ... no FP16 support, no Nvlink ( only compatiblle with IBM chipset anyway ( outside GPU to GPU ). And i soomewhat can imagine that the most "available " one on Q4 will be the salvaged one. ( due to HBM2 )
As for double precision, i dont know, AMD have been at 1:2 rate since a lot of time.... so if they keep up with it, i dont see much trouble in term of performance for them.. ofc, all depend the direction they have to take ....
As for double precision, i dont know, AMD have been at 1:2 rate since a lot of time.... so if they keep up with it, i dont see much trouble in term of performance for them.. ofc, all depend the direction they have to take ....
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Thaiti (GCN1.0 ) had 1:4DP ( both Firepro and 7970 )... .
Hawaii have initiate the 1:2 DP rate but only on Firepro , server version, the gaming Hawaii had a DP rate artificially set in softtware at 1:8 ( 290 series ). ( Firepro W9100, W81000 had 1:2 )
( FirePro W9100, March 2014, Hawaii, GCN1.1, 28nm, SP 5237.8Gflops, DP 2618.9Gflops )
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The HPC APU slide gives a Greenland GPU with >4 TFLOPs, and half-rate double precision. It sounds like Fiji without hobbled double precision, and probably would be smaller due to the node an having only 2 stacks of HBM2.
There are elements to the current GCN ISA that allow for some of the handling of the different precisions used by deep learning, but I haven't seen much of AMD targeting it.
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Im not quite sure, that AMD want to target it right now .. maybe after Vega ... Not that they have no interest to do it, but i think they have set their priority to take back share on " larger base of server and workstation" for Vega.. instead of deploying energy ( and money ) for Deep learning .. ( specially on the software ecosystem ) .
I could be wrong, and that dont mean they have nothing in this regard ready, just that in their actual state, they need to fix some priority, and even if their hardware is capable of it, dont go frontal in the market of Deep AI learning ( specially when today, lets be honest, specialized architectue are way better than what we could see with "GPU's use "arch" who are made as it, is maybe better than trying to simulate thoses arch. ) Using Neuronal architecture is surely better than any gpu's ..
( offcourse i like the work of Nvidia with Deepl, but honestly i think the future of it outside execution is on specialized processors, if you want to simulate neuronal activitty, you need neuronal processors who are really able to simullate it, simple as that., and at this rate, not even an ExaFlops system willl be able to do it correctly with gpu's.. )
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There are inefficiencies to multiple sites, but it's hard to find enough talent in one location so better talent trumps inefficiency much of the time. NV's main campus in California is larger than any single AMD RTG site, but they still have design offices all over the world including many of the same locations as AMD. Shanghai, Austin, Boston, etc.
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