The latest LLVM patch confirms the increased register size for N31/N32. And it also says that the allocation granularity went up by 50% (24/12 vGPRs in Wave32/64 mode instead of 16/8 vGPRs or 8/4 vGPRs with RDNA1). This implies also 50% more register banks (instead of larger banks) and therefore more register bandwidth to satisfy the VOPD instructions (and potential co-issue of two vector instructions from two wavefronts).