Van Gogh was 7-9W APU. Rembrandt is 15-65W APU. It's like saying that RTX 3060 is not needed because RTX 3090 eats it for breakfast.
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I don't think it will eat its breakfast. Rembrandt has no Infinity Cache:
Furthermore purely going from 8->12 CUs will not matter that much at low TDP (maybe 10-20% diff at 15W?), it will probably really matter at higher TDP where the extra +50% CUs results in a significantly higher performance ceiling. The CPU generally doesn't really matter as all the power is eaten by the GPU and at the low end Zen2 can decently keep up with Zen3. I have some concerns about only having 4 cores wrt possible stutters when games try to do something depending on how fast CPU reclocking kicks in but I think that will only matter in very select games, and have a reduced impact due to most games only being able to run at 30 fps due to GPU performance.
If they can get VanGogh at a significantly cheaper price than Rembrandt it might be totally worth it. Sure it won't be the top product but it might go a significant direction in making these devices cheaper and hence more accessible. (As an aside I doubt X3D is going to be cheap for a bit)
Bondrewd
Veteran
Only 50mm^2 smaller and is a niche part.
It was never made for lowend turdflinging.
AMD has a different part planned for that.
I think price isn't just die size. AMD seems to mostly price their older gens significantly discounted but still supported. Think Lucienne and Barcelo. Just my speculation here but I wouldn't be surprised if VanGogh could be significantly cheaper here.
Bondrewd
Veteran
Oh it is.
Not TSMC parts really.
Those are just embedded padding.
Jfc it is labeled under "premium FF" for a reason.
It's the expensive part of the bunch.
I'm aware it was labeled for premium FF, with stuff like NN acceleration specifically for these usecases. However AFAICT Rembrandt is AFAICT pretty much a superset of VanGogh with the same features (edit: besides the changed CPU setup obviously). So I'm not sure what would make these chips particularly expensive outside of the target market (which I think we can agree on is to be thrown out at this point).
D
Deleted member 13524
Guest
Then that's a damn shame because memory bandwidth is pretty much the only thing preventing AMD from developing high performance APUs for laptops and DIYs.
Bondrewd
Veteran
Was priced as such too,
Two very different segments and packages.
Think late'23 timeline for maybe pile-o-SRAM in APUs.
Bondrewd
Veteran
They're W6800 and W6600.
Basically N21/23 but Radeon Pro.
https://videocardz.com/newz/sk-hynix-expects-hbm3-memory-with-665-gb-s-bandwidth
I was wondering if on a rdna3 refresh, or even rdna4, having already afforded the cost for a substrate, and being less reliant on pure BW, they can add a single hbm3 die, maybe one of the ~800MB/s flavour...
I was wondering if on a rdna3 refresh, or even rdna4, having already afforded the cost for a substrate, and being less reliant on pure BW, they can add a single hbm3 die, maybe one of the ~800MB/s flavour...
Bondrewd
Veteran
Jawed
Legend
If this new core design features a "solution" to the thread-divergence problem, that would be sweet. It would have a major impact on ray tracing too.
How likely is it that RDNA3 will include dedicated tessellation hardware? Between mesh shaders and high poly methods like Nanite it seems fixed function tessellation is on its way out. Are GPUs fast enough now to run DirectX tessellation in software at reasonable performance?
Jawed
Legend
I'd say it's pretty likely to have tessellation hardware on the basis that it's not much die area.
Though I can't remember ever successfully identifying an area of a die image that seems to be the tessellator.
You can take a die shot and find a "neatly bordered" area and call it the tessellator for all the difference it makes and then find that it's less than 1% of the die's area. A typical AMD GPU die shot has dozens of these neatly bordered areas outside of the CUs. Many of them repeat many times so can be ignored (e.g. ROPs or caches). The remaining neatly bordered areas, any of which could be the tessellator (or one out of a small set, e.g. 2 or 4) are never that large.
This hardware should be "off" when not being used. So wasted power isn't a reason to delete.
Overall it seems like a low priority to convert this to a software emulation, especially as it would require driver work.
I dont‘t think so. Rasterising is a special step. Maybe we se next time a Rasterizer which suites more Engines like Nanite. The Rasterizer area should be much smaller and efficient than the software shader rasterizer. If you see patents we are at the beginning of changing the Frontend. I think major steps come with chipset design.
This patent sounds like Nanite:
https://www.freepatentsonline.com/10957094.html
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