AMD: R7xx Speculation

[w0mbat]

More funny is that the first speculations on hartware.de already had the 96v5 (480) info. Maybe they´ll be right at all (apart from some lower clks).

 

[HAL]

8800GT will be replaced by 9800GT.

There are 3 possibilities:
1. 9800 GT aka GTS 260; 9800 GTX aka GTS 280.
2. 9800 GT aka GTS 240; 9800 GTX aka GTS 260; xxx aka GTS 280
3. no more 9800 GT; 9800 GTX aka GTS 260; xxx aka GTS 280
xxx = Better card than 9800 GTX.
However manufactured by 55 nm productive process.
IMHO

 

[AnarchX]

9800 GT is G92(B) based SKU with just a little higher clock than 8800 GT, 112SP+650/1000MHz is rumored.

 

[w0mbat]

Another thought:

160x5 = 800
800x625 = 1 TFLOP

AND

160x3 = 480
480x1050 ~ 1 TFLOP

Even if everyone here is going for 480SPs, which seems to be more likely, im not quiet shure yet. Im not an GPU engineer and i dont know how easy u could change rv670, but im not convinced yet that it has to be 96v5 shaders.

 

[CarstenS]

That's what w1zzard proposed some days ago

 

[w0mbat]

So do u think 160v3 is possible?

 

[trinibwoy]

If it's 480 it is going to be 96*5. vec3 makes absolutely no sense.

 

[w0mbat]

And why?

 

[Lukfi]

They must have had a reason to go from vec3 (IIRC) to vec5 in the first place, why would they go back now?

 

[leoneazzurro]

And why?

IIRC, a vec5 superscalar works better on vertex workloads and is not so much bigger than a vec 3 superscalar unit.

 

[Sound_Card]

I wonder if RV770 will have 6 SIMD arrays(two more four quad arrays) going to 6 RBE's to keep a nice and neat pattern eh? Or perhaps most likely they are going to stay at 4 RBE's and just let the shader export distibute accordingly. Or will they even stay at 4 SIMD arrays with just two more quads added to each array?

 

[Lukfi]

I thought R600 and RV670 no longer have four arrays of something. These chips have 64 shaders, but RV610 has 8 and RV630 has 24. That would mean there are 8 arrays of 8 units in R600/RV670, not 4 arrays of 16 units, if my reasoning is correct. But to answer your question, I think that with 6 RBE blocks it would be impossible to keep the memory bus width at 256 (or any other 2^n number) bits. The ratio between shaders and RBEs is not fixed, so they can stay at 4 RBE blocks.

 

[Tchock]

They must have had a reason to go from vec3 (IIRC) to vec5 in the first place, why would they go back now?

IMHO Vertex processing power is rather abundant and overkill-esque in the current R6XX configs already.

160 v3 instead of 96 v5 should help in the bad/worst case utilization scenarios, but if ATI already went so far to do this the other issues would have been squished, squashed, and squoshed too.

 

[w0mbat]

Or we really get 160v5 shaders which will give us 1 tflop w/ only 625mhz. Im curious about the first real leak about the shaders, hope it will be soon.

 

[HAL]

http://www.nordichardware.com/news,7755.html

4850 625/2000.
4870 725/3920.

 

[Lukfi]

You know what's funny? That all this originated in this very thread

 

[mczak]

I thought R600 and RV670 no longer have four arrays of something. These chips have 64 shaders, but RV610 has 8 and RV630 has 24. That would mean there are 8 arrays of 8 units in R600/RV670, not 4 arrays of 16 units, if my reasoning is correct.

err, no you're very wrong here... RV670 (and R60) certainly has 4 shader arrays with 16 5-wide units each. RV630 has 3 shader arrays with 8 5-wide units. RV610 has 2 arrays with 4 units each. Remember unlike G80/G9x array length is not fixed!
I don't know neither though if it will be 6 arrays with 16 units or 4 arrays with 24 units - if it's really going to have 32 tmus (well 16 would also be possible but in this case but I think everybody ruled that out...), it must be 6 arrays with 16 units, else if it's going to have 24 tmus, it must be 4 arrays of 24 units due to the way tmus are coupled to the shader arrays.

But to answer your question, I think that with 6 RBE blocks it would be impossible to keep the memory bus width at 256 (or any other 2^n number) bits.

Again unlike G80/G9x, RBEs are not directly coupled to memory channels (R600 still only had 4 RBEs despite having 512bit bus), so it should be possible, though I think most consider it unlikely.

The ratio between shaders and RBEs is not fixed, so they can stay at 4 RBE blocks.

Yes, certainly.

 

[Jawed]

I'm holding steadfastly to 16 TUs.

Jawed

 

[Sound_Card]

I thought R600 and RV670 no longer have four arrays of something. These chips have 64 shaders, but RV610 has 8 and RV630 has 24. That would mean there are 8 arrays of 8 units in R600/RV670, not 4 arrays of 16 units, if my reasoning is correct. But to answer your question, I think that with 6 RBE blocks it would be impossible to keep the memory bus width at 256 (or any other 2^n number) bits. The ratio between shaders and RBEs is not fixed, so they can stay at 4 RBE blocks.

As pointed out already no. RV670 has four SIMD arrays of 16 5 wide shaders(4 quads).

I'm also under the impression that the RBE's are not tied into the MC's.

 

[w0mbat]

I'm holding steadfastly to 16 TUs.

Jawed

And w/ TUs u mean what? I only know TMUs.