hoom
Veteran
Just thought I should point out something regarding non-power of 2 scaling of TMU/ROP/ALU clusters:
People seem to be forgetting the ring bus.
In R600/RV670 there are 4 main ring bus stops, each serving an ALU cluster, a ROP quad, a TMU quad and with either a 64 or 128bit memory controller connected to either 2 or 4 RAM chips.
Assuming that there haven't been major changes to this basic architecture:
-To have 5 ALU clusters there needs to be a 5th ringstop, which would mean a combined 320bit bus, 20 TMUs, 20 ROPs & 10 RAM chips.
-To have 24 TMUs there needs to be 2 more ringstops, which means 384bit bus, 24 ROPs & 12 RAM chips.
Both would also produce increased system latency on the ringbus.
The pics of 4850 card show only 8 RAM chips (& there has been no rumor of other than 256bit/512bit) so there must be either only 4 ringstops or its been power of 2ed to 8 ringstops.
People seem to be forgetting the ring bus.
In R600/RV670 there are 4 main ring bus stops, each serving an ALU cluster, a ROP quad, a TMU quad and with either a 64 or 128bit memory controller connected to either 2 or 4 RAM chips.
Assuming that there haven't been major changes to this basic architecture:
-To have 5 ALU clusters there needs to be a 5th ringstop, which would mean a combined 320bit bus, 20 TMUs, 20 ROPs & 10 RAM chips.
-To have 24 TMUs there needs to be 2 more ringstops, which means 384bit bus, 24 ROPs & 12 RAM chips.
Both would also produce increased system latency on the ringbus.
The pics of 4850 card show only 8 RAM chips (& there has been no rumor of other than 256bit/512bit) so there must be either only 4 ringstops or its been power of 2ed to 8 ringstops.