gasp, a new, mysterious source calling itself "PhotoChopCS3" just uploaded a secret picture of R700 magic fairies sent me earlier straight from AMD
OMG... 2008 doesn't look to bright for AMD.
R700 in 2009?! no Shanghai, nor FUSION in 2008 or early 2009
oh boy
The problem with something like this is that you need a crapload of connection pads on that "central memory controller". That's why a distributed memory controller in a ring-bus type of layout seems more plausible to me.4 cores + 1 "hub" with "central memory controller" and some other functions like i/o etc?
The problem with something like this is that you need a crapload of connection pads on that "central memory controller". That's why a distributed memory controller in a ring-bus type of layout seems more plausible to me.
Even that is tough, though. How do you distribute the load? Anything with stencil buffers, alpha blending, or occlusion query requires you to rasterize polygons sequentially unless they cover different pixels.
Multichip GPUs that don't rely on AFR are very tough to implement because you have to find a point in the 3D pipeline where the data flow is not overwhelming. Xenos found a narrow point before the ROPs where data flow of 16GB/s could translate into memory BW of up to 256GB/s, thus allowing for a split of dies. Distributing shader load across chips is a much more difficult task.
R700 in 2009?! no Shanghai, nor FUSION in 2008 or early 2009
oh boy
I'm not completely sure a single 1.2 billion chip is as easy to make as most ppl seem to believe. Or, more adequately, made to yield in an even remotely satisfactory fashion. Scaling may also be a pain. With the smaller 300 million chips your yields would be awesome(per the small chip), and scaling would be far easier to achieve(from butt-end 1 chip configs to the fizzle my shnizzle 4 chip ones).
OTOH, there are issues that have to be tackled in a multi-chip approach(many of which have already been discussed before in this thread), so it's not a walk in the park either.
OK, well let me put it another way, what would be the point if it was 1.2 billion across two chips, since that would be near as daamit (sorry) the r680 (GX2) anyway, so which ever way you spin it, its got to come out as a distribution of at least 1.6 to 1.8 billion. other wise you may as well only just stick with r680, or a single die with 1.2 - 1.3 billion transistors.
Transistor counts don't tell the whole story, do they?The R600 had a crapload of trannies and it was fairly sucky. I'm not necessarily contradicting your assumption, but if it ends up in that area I don't think the cause would be that they simply wanted to have more trannies.
The only real advantage I see is you only have to develop 1 chip for all your SKUs.
Ex: low end - 1 chip, midrange - 2 chips, high end 4 chips
As for some R700 speculation - 64bit external / 256bit internal per chip