AMD: R7xx Speculation

Status
Not open for further replies.
rr77.jpg


GPU0-3 : pure graphics processors
IO : UVD,PCI-E,RAMDAC,etc

If 4 die GPU is true, it might look like very well for Opteron.
 
Last edited by a moderator:
gasp, a new, mysterious source calling itself "PhotoChopCS3" just uploaded a secret picture of R700 magic fairies sent me earlier straight from AMD
:oops:

r700wip34.jpg
 
OMG... 2008 doesn't look to bright for AMD.

R700 in 2009?! no Shanghai, nor FUSION in 2008 or early 2009

oh boy
 
Shanghai wouldn't fit under the desktop or enthusiast categories, and the 45nm Deneb and Propus are listed in 2H 08.

I believe the idea as that the server chips would transition first, so Shanghai should beat them to market (though 2H 08 for desktop might be 4Q 08).

What the heck is the R6xxTM GPU entry though?

If it's a minor revision or dual-chip variant of RV670, then that means R600's lineage will stretch nearly 2 years before an actual redesign takes place.
 
OMG... 2008 doesn't look to bright for AMD.

R700 in 2009?! no Shanghai, nor FUSION in 2008 or early 2009

oh boy

Neithwe Shanghai nor Fusion would be on the Enthusiast Platform roadmap. And we really don´t khow fast the new R6xx parts will be (OK I would not be surprised if the fastest card would be dual RV670 shrink with a few tweaks).
 
I really hope that's FUD.

If it's true, AMD may as well just throw in the towel, because if their 8-core design (Montreal) and R700 won't be out until 2009 then they have ZERO chance of being even remotely competitive in 2008, and have only a slim chance of being competitive in 2009.

I used to hate the term "DAAMIT" but it couldn't be truer now. It's all I think of anymore anytime I think about AMD.

DAAMIT, AMD.
 
4 cores + 1 "hub" with "central memory controller" and some other functions like i/o etc?
The problem with something like this is that you need a crapload of connection pads on that "central memory controller". That's why a distributed memory controller in a ring-bus type of layout seems more plausible to me.

Even that is tough, though. How do you distribute the load? Anything with stencil buffers, alpha blending, or occlusion query requires you to rasterize polygons sequentially unless they cover different pixels.

Multichip GPUs that don't rely on AFR are very tough to implement because you have to find a point in the 3D pipeline where the data flow is not overwhelming. Xenos found a narrow point before the ROPs where data flow of 16GB/s could translate into memory BW of up to 256GB/s, thus allowing for a split of dies. Distributing shader load across chips is a much more difficult task.
 
The problem with something like this is that you need a crapload of connection pads on that "central memory controller". That's why a distributed memory controller in a ring-bus type of layout seems more plausible to me.

Even that is tough, though. How do you distribute the load? Anything with stencil buffers, alpha blending, or occlusion query requires you to rasterize polygons sequentially unless they cover different pixels.

Multichip GPUs that don't rely on AFR are very tough to implement because you have to find a point in the 3D pipeline where the data flow is not overwhelming. Xenos found a narrow point before the ROPs where data flow of 16GB/s could translate into memory BW of up to 256GB/s, thus allowing for a split of dies. Distributing shader load across chips is a much more difficult task.

So perhaps we should be talking about R700 multi-die with a separate ROP/EDRAM die? I know to some this may seem like a regression rather than progress, but given the right mix of hardware & clockspeeds it's still a viable option if you ask me.
 
I was wondering about R700-multi design, so is that means it will perform slow for the older games which meant for single GPU platform.
 
R700 in 2009?! no Shanghai, nor FUSION in 2008 or early 2009
oh boy

Well, it is a real slide I'm sad to say but I think there is some sort of mixup.
Please note it does say "R7xx Family" and that on another slide they state "R7xx FireGL" in the same timeframe, FireGL cards usually come out quite a few months after the normal consumer lineup.
 
I suppose the upside to this is that a year-long delay would not be due to a manufacturing issue in all likelihood, which implies that the original R700 design has been scrapped and a revised design is in the works, which further implies that ATi has targeted new (higher) performance levels. That can only be a good thing, and very much needed given their recent track record.
 
Slide is real and comes from the analyst meeting yesterday.

Download here for full details:

http://download.amd.com/Corporate/MarioRivasDec2007AMDAnalystDay.pdf

It's not just R700 that has been pushed out. The new Bulldozer core has been dropped from the 2009 roadmap, too. This is from the WSJ:

"In one change disclosed yesterday, AMD is adjusting a plan dubbed Fusion to combine its computing circuitry with ATI's graphics technology on a single chip. In July, AMD said the first product from that effort would use a sophisticated new microprocessor design, code-named Bulldozer.

Now AMD plans to make its first multi-function chip using modifications of an existing microprocessor, in a product called Swift that will arrive in mid-2009. In an interview, Mr. Ruiz said customers wanted AMD to reduce design risks and deliver a product sooner. "

Anyway, no mention of the Bulldozer core on any of the roadmaps released yesterday. Barcelona can't compete with today's Core 2 architecture, much less a second gen Nehalem core. By the end of 2010 things will be utterly miserable.
 
I'm not completely sure a single 1.2 billion chip is as easy to make as most ppl seem to believe. Or, more adequately, made to yield in an even remotely satisfactory fashion. Scaling may also be a pain. With the smaller 300 million chips your yields would be awesome(per the small chip), and scaling would be far easier to achieve(from butt-end 1 chip configs to the fizzle my shnizzle 4 chip ones).

OTOH, there are issues that have to be tackled in a multi-chip approach(many of which have already been discussed before in this thread), so it's not a walk in the park either.

OK, well let me put it another way, what would be the point if it was 1.2 billion across two chips, since that would be near as daamit (sorry) the r680 (GX2) anyway, so which ever way you spin it, its got to come out as a distribution of at least 1.6 to 1.8 billion. other wise you may as well only just stick with r680, or a single die with 1.2 - 1.3 billion transistors.
 
OK, well let me put it another way, what would be the point if it was 1.2 billion across two chips, since that would be near as daamit (sorry) the r680 (GX2) anyway, so which ever way you spin it, its got to come out as a distribution of at least 1.6 to 1.8 billion. other wise you may as well only just stick with r680, or a single die with 1.2 - 1.3 billion transistors.

Transistor counts don't tell the whole story, do they?The R600 had a crapload of trannies and it was fairly sucky. I'm not necessarily contradicting your assumption, but if it ends up in that area I don't think the cause would be that they simply wanted to have more trannies.;)
 
Transistor counts don't tell the whole story, do they?The R600 had a crapload of trannies and it was fairly sucky. I'm not necessarily contradicting your assumption, but if it ends up in that area I don't think the cause would be that they simply wanted to have more trannies.;)

right..., but it would be better to have one sucky r600. than having the same sucky architecture broken in to four pieces, at the same total transistor count.

If going multi chip is not bout being able to have more transistors, within a fabrication process, then what else is the point? its certainly not because its more efficient to do so is it?
 
The only real advantage I see is you only have to develop 1 chip for all your SKUs.

Ex: low end - 1 chip, midrange - 2 chips, high end 4 chips

As for some R700 speculation - 64bit external / 256bit internal per chip
 
The only real advantage I see is you only have to develop 1 chip for all your SKUs.

Ex: low end - 1 chip, midrange - 2 chips, high end 4 chips

As for some R700 speculation - 64bit external / 256bit internal per chip

I don't know if it's worth it to have a single chip multiplied..., and then be entirely dependent of a number of different core packages, PCB layouts, coolers, memories types and amounts, etc...
 
Status
Not open for further replies.
Back
Top