AMD: R7xx Speculation

[Rangers]

I really think AMD might have a real winner on it's hands. If the die is anywhere near as small as some of the impressions. This thing could be fast and cheap, and the fact it pushes more flops than GT200 is an eyeopener (even though we know we wont see performance superiority in games). And all it took was 32 TMU's..

The chart is listing 850 core/1050 shader on 4870..hmmm.

 

[mao5]

AMD castrated the speed of RV770Pro2008-5-26 18:36:25AIB graphics cards marker told us that AMD had castrated the core speed of RV770Pro.

We’ve reported that the core speed of RV770Pro graphics chip can be reached at 990MHz (http://www.pczilla.net/en/post/4.html). But now AMD set the speed of retail version of RV770pro at 625MHz. AIB graphics cards marker told us this is the marketing strategy, in order to get the performance difference between RV770Pro、RV770XT and HD3870.

According to the AMD's reference design manual seen by AIB graphics cards markers, RV770Pro design frequency went beyond 900 MHz, that is when RV770Pro run in the 900 MHz frequency is only when the frequency of its design, and the 625 MHz frequency is obviously down to use.

Considering the Power play function and energy-saving features integrated in RV770Pro, so in some cases the core speed of Radeon HD 4850 will be even lower than the frequency of 400 MHz.

Radeon HD 4850 graphics card will equipped with 512 MB GDDR3 memory with 1ns speed, if its core speed runs at 900MHz frequency, its effectiveness will obviously go beyond the current Radeon HD3870, for this, AMD limited the first batch of public version of the Radeon HD4850, AMD will not allow AIB to ship Radeon HD4850 with overclocking out of box. This decision clearly shows HD4850 to be cost-effective products in this summer.

http://www.pczilla.net/en/post/24.html

 

[CarstenS]

Unless they've had an abundant amount of redundancy in RV670 - which i also doubt given the shrinkage from R600 - i do believe in either 32 FP16-TMUs and a separate shader clock when i see it.

But even without both, but only with fixed ROPs, RV770 should be the fastest chip yet - IMHLO.

 

[trinibwoy]

Boards photos.

On a quick note: dual 6-pin power inputs for the HD4870 SKU.

Nice! Glad to see somebody at ATi finally figured out how to make a good looking cooler. All they needed was a little black to go with the red

They flipped the TMU's and ROPS for the GeForces on that chart. Though I think G80 Ultra was only 32 TMU's as well

32 TA / 64 TF

 

[mboeller]

regarding the R700 / 48x0 X2:

quoting wiki:

HyperTransport....Year....Max. HT Frequency....Max. Link Width....Max. Aggregate Bandwidth
Version..............................................................................................(bi-directional)
3.0.......................2006..........2.6 GHz........................32 Bit..................41.6 GB/s


so 2 HT3.0 links would be sufficient, or?

 

[w0mbat]

AFAIK, R700XT still uses a PLX chip for interconnection.

 

[Lukfi]

It appears so. The cooler says it all.

 

[Lux_]

2 HT3.0 links would be sufficient, or?

I have my doubts regarding successful implementation of such interconnect: AMD's own implementation got delayed until Shanghai.

 

[Mat3]

One question still bothering about the truth RV770 480Streams.

A. Is RV770 480 ALU's is packed into groups of 5:1 is 96+384 = 480 streams.

-OR-

B. Is RV770 480 ALU's is packed into groups of 3:1 is 160+320 = 480 streams.

Which solution is more efficient and faster?

Going in packs of three probably doesn't make much sense. DX9 pixel shaders were all designed for dual issue vec3 + scalar or dual issue vec2s. They went with five because of vertex shaders (typical vec4 + 1) but if they were designing with only pixel shaders in mind, I would guess four (or two?) would be the ideal number since a lot of stuff could still be packed into four.

Regardless, it's extremely doubtful there'll be any change to the ALU structure this time around.

 

[mao5]

Anyone notices that Radeon HD 4000 series support Physics and ray tracing?

 

[AnarchX]

Anyone notices that Radeon HD 4000 series support Physics and ray tracing?

R300 also could do it.

 

[BRiT]

Anyone notices that Radeon HD 4000 series support Physics and ray tracing?

But AMD declared GPU Physics Dead for Now.

 

[Rangers]

But AMD declared GPU Physics Dead for Now.

Well they were certainly right so far.

 

[Lux_]

Anyone notices that Radeon HD 4000 series support Physics?

Radeon could do it if someone would take up the task to code it in (using CAL). But NVidia went and coded it into Unreal Engine 3 (using CUDA).
So, cards from both companies have the "capability" for it, but guess whose cards end up accelerating it for real?

Same is true for raytracing - both AMD and NVidia produce cards that could be used to speed up raytracing. But unfortunately it seems that only one company has the resources to wrap these capabilities into nice and convenient wrapper.

 

[Lukfi]

Anyone notices that Radeon HD 4000 series support Physics and ray tracing?

I noticed, but discarded it as marketing clutter.

 

[Rangers]

Anyone notices that Radeon HD 4000 series support Physics and ray tracing?

Does the custom AA part of that slide confirm AA still done in shaders?

 

[AlexV]

Does the custom AA part of that slide confirm AA still done in shaders?

No. Any DX10 card should be and is capable of implementing custom resolve, and by extension, solutions similar to CFAA.

 

[whocares]

What's the TeraScale engine?

I also ask what's that ?

 

[AlphaWolf]

I'm gonna guess terascale has something to do with the number of operations per second.

 

[mczak]

I have my doubts regarding successful implementation of such interconnect: AMD's own implementation got delayed until Shanghai.

It should be quite a bit simpler for connecting "only" 2 (graphic) chips sitting right next to each other (tighter control over signal delays etc., and probably you wouldn't need the cache-coherence part neither).
I'm not sure how much bandwidth you'd actually need between the two graphic chips to make this semi-transparent performance-wise? Obviously, each chip would still use its own memory for color/z-buffer even if not AFR but super-tiling would be used.