Xbox One (Durango) Technical hardware investigation

[french toast]

Dissapointing. Was hoping for something special here to help close the gap.

 

[DJ12]

So no secret sauce. Maybe this terrible term can now be put to bed. Microsoft have a plan and they are sticking to it.

The real selling point will only become apparent at the reveal and in my opinion it will be the OS features

 

[dragonelite]

So no secret sauce. Maybe this terrible term can now be put to bed. Microsoft have a plan and they are sticking to it.

The real selling point will only become apparent at the reveal and in my opinion it will be the OS features

Ooh shit and rumor has it they are gonna bait and switch at their press event and E3.
Gonna keep my eyes out and probably not get it day one. With all those shady rumors.

 

[HollovVpo1nt]

Why would Microsoft hire all those SoC engineers and then use a stock Jaguar CPU? I guess they must be working on Surface Phone or a new Surface or something...

 

[MBDF]

"sixteen 256-bit vector/SIMD registers"

I'm guessing this isn't significant eh?

 

[Betanumerical]

"sixteen 256-bit vector/SIMD registers"

I'm guessing this isn't significant eh?

http://en.wikipedia.org/wiki/Advanced_Vector_Extensions

Standard AVX.

 

[tunafish]

"sixteen 256-bit vector/SIMD registers"

I'm guessing this isn't significant eh?

That's just the AVX registers. In reality they are implemented as two 128-bit registers each. All Jaguars have them.

 

[Strange]

Guess I was pretty much right.

2 vanillas (essentially) taped together to get twice the performance of a vanilla Jaguar (just like the PS4).

Don't think I saw an there that magically allowed the 720 CPU to do twice the Flops of PS4 CPU. Some misinterpretation perhaps in the earlier leaks perhaps?

Durango CPU cores have dual x64 instruction decoders, so they can decode two instructions per cycle. On average, an x86 instruction is converted to 1.7 micro-operations, and many common x64 instructions are converted to 1 micro-operation. In the right conditions, the processor can simultaneously issue six micro-operations: a load, a store, two ALU, and two vector floating point. The core has corresponding pipelines: two identical 64-bit ALU pipelines, two 128-bit vector float pipelines (one with float multiply, one with float add), one load pipeline, and one store pipeline. A core can retire 2 micro-operations a cycle.

In one cycle, 2 128 bit vector float pipelines, two vector floating point operations. And dual 2 instructions per cycle all adding up to 8 FLOPS a cycle.

Don't think I see anything that can allow it to be beefed up to 16 FLOPS a cycle.

 

[Hornet]

Latency of a remote L2 hit is pretty bad. I wonder how hard it would have been to implement a shared L2 cache.

 

[expletive]

Weird, multiple non-vgleaks sources say the CPU in Durango is different (with most of those saying more powerful) than orbis but this looks pretty much the same.

 

[Brad Grenz]

Weird, multiple non-vgleaks sources say the CPU in Durango is different (with most of those saying more powerful) than orbis but this looks pretty much the same.

Multiple self-appointed insiders who didn't understand what they were reading thought the "double pumped" 256bit AVX capabilities meant something it didn't. Same with the "insiders" who didn't understand all the ancient GPU technologies they were reading about and assumed were proprietary to the Durango.

 

[Strange]

Weird, multiple non-vgleaks sources say the CPU in Durango is different (with most of those saying more powerful) than orbis but this looks pretty much the same.

My take on it is that they're probably comparing it to a vanilla 4 core Jaguar and concluded that the Durango CPU is 2x as good as Jaguar. Only Orbis is also double a vanilla Jaguar, so you're ending up with the same thing.

I think the "twice as powerful" that we've been seeing from multiple sources indicate that this misconception might be not too far fetched.

 

[oramay]

Weird, multiple non-vgleaks sources say the CPU in Durango is different (with most of those saying more powerful) than orbis but this looks pretty much the same.

Do you mean forum posters who have a tendency to inject their own interpretation and speculation into their "information"?

 

[function]

No mention of low latency esram access, at least for the CPU. Special sauce: denied.

 

[Love_In_Rio]

No mention of low latency esram access, at least for the CPU. Special sauce: denied.

In fact L2 miss to L2 hit latencies are pretty bad. So L2 miss to L2 miss to ESRAM hit will be even worse. At least they will be better than to DDR3 hit.

 

[SenjutsuSage]

No mention of low latency esram access, at least for the CPU. Special sauce: denied.

I was under the impression that the GPU article stated pretty clearly that the CPU doesn't even contend for the ESRAM's memory in the first place, so why would anyone expect something that was clearly said to not happen, suddenly be expected to be some "secret sauce?" I'm confused.

 

[Love_In_Rio]

I was under the impression that the GPU article stated pretty clearly that the CPU doesn't even contend for the ESRAM's memory in the first place, so why would anyone expect something that was clearly said to not happen, suddenly be expected to be some "secret sauce?" I'm confused.

It seems the advantages of ESRAM are more oriented to GPU compute ops latency.

 

[SenjutsuSage]

It seems the advantages of ESRAM are more oriented to GPU compute ops.

I was under the impression that this was always expected to be the case. I get the feeling that people are looking for reasons to pile onto the new xbox.

 

[function]

In fact L2 miss to L2 hit latencies are pretty bad. So L2 miss to L2 miss to ESRAM hit will be even worse. At least they will be better than to DDR3 hit.

I don't understand how a L1 & L2 cache hit on the other module makes latency worse than just a L2 cache hit on the other module.

I was under the impression that the GPU article stated pretty clearly that the CPU doesn't even contend for the ESRAM's memory in the first place, so why would anyone expect something that was clearly said to not happen, suddenly be expected to be some "secret sauce?" I'm confused.

I thought the CPU was supposed to be able to access the esram. Maybe it can't.

Edit: this diagram made me think the CPU could access the esram though the NB: http://forum.beyond3d.com/showpost.php?p=1696577&postcount=2

 

[SenjutsuSage]

http://www.vgleaks.com/durango-gpu-2/2/

The difference in throughput between ESRAM and main RAM is moderate: 102.4 GB/sec versus 68 GB/sec. The advantages of ESRAM are lower latency and lack of contention from other memory clients—for instance the CPU, I/O, and display output. Low latency is particularly important for sustaining peak performance of the color blocks (CBs) and depth blocks (DBs).