I thought the CPU was supposed to be able to access the esram. Maybe it can't.
I don't see why it matters either way.
DDR3 was supposed to be well suited for the CPU so what's exactly the benefit of having an extra high bandwidth eSRAM?
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I thought the CPU was supposed to be able to access the esram. Maybe it can't.
I don't understand how a L1 & L2 cache hit on the other module makes latency worse than just a L2 cache hit on the other module.
Edit: this diagram made me think the CPU could access the esram though the NB: http://forum.beyond3d.com/showpost.php?p=1696577&postcount=2
I don't think that the "CPU works really well with DDR3" means much. I think that a L2 might be a disaster as far as performances are concerned, with hundred of cycles lost. The OoO execution engine is far from being able to hide those kind of latencies.Yea, the CPU will work very well with DDR3. The esram is clearly there for the purpose of benefitting the GPU.
I don't think that the "CPU works really well with DDR3" means much. I think that a L2 might be a disaster as far as performances are concerned, with hundred of cycles lost. The OoO execution engine is far from being able to hide those kind of latencies.
Having scratchpad+move engines accessible by the CPU would have been nice, though feeding the GPU might have been the priority (rightly though).
Why do you say ESRAM is not accessible by the CPU?. It is ( and coherent access for GPGPU greatness ), through the northbridge and GPU memory system.
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I don't understand how a L1 & L2 cache hit on the other module makes latency worse than just a L2 cache hit on the other module.
Well from VGleaks in the ESRAM part.Why do you say ESRAM is not accessible by the CPU?. It is ( and coherent access for GPGPU greatness ), through the northbridge and GPU memory system.
Hmm. Is there any chance this CPU is being builded with 2 banks of 4 ARM Cortex cores?
Maybe something like the ARM Cortex A57?
Cortex-A57 at a Glance
http://vr-zone.com/articles/arm-int...x-a53-and-cortex-a57/17652.html#ixzz2MGHFDGW7
- Out-of-Order ARMv8 32/64 Core
- Up to Quad-Core Design
- 44-bit Virtual Memory Address
- Up to 16TB RAM (LPDDR3 to DDR4)
- 48KB L1 I-Cache (w/DED parity)
- 32KB L1 D-Cache (w/ECC)
- NEON SIMD Engine
- FPU
- 128KB - 2MB L2 Cache (w/ECC)
- 128-bit CoreLink Interconnect (CCI-400 and CCN-504)
http://www.xbitlabs.com/news/cpu/di...res_Cortex_A53_and_Cortex_A57_Make_Debut.html
More likely the even smaller A5 (A7 tops). And yes, AMD stated that their APUs/SoCs will support Trustzone starting in 2013. If that applies already to Kabini or only Kaveri? No idea.There definetly was a rumor that MS is going with ARM Cortex for TrustZone (I'm don't know whether it's still up to date) and it would be no problem for AMD to integrate it into the XBox APU. But TrustZone on consumer APUs will happen with Cortex A9 cores and not with A57 cores.
More likely the even smaller A5 (A7 tops). And yes, AMD stated that their APUs/SoCs will support Trustzone starting in 2013. If that applies already to Kabini or only Kaveri? No idea.
More likely the even smaller A5 (A7 tops). And yes, AMD stated that their APUs/SoCs will support Trustzone starting in 2013. If that applies already to Kabini or only Kaveri? No idea.
I wouldn't be surprised if some kind of "hypervisor" stack is running on an ARM core on both Orbis and Durango doing authentication stuff at start-up (integrity check), Bluray security and checking games' disks etc next to acting as some kind of sleep mode processor.
But... keep in mind TrustZone for the CPU is nothing more than an extra CPU state, next to e.g. user mode and privilege mode... with the difference that you can limit to peripherals (e.g. a RTC timer) to Trustzone mode only... meaning that it's harder to tamper with security-related HW.
Why no one questions Vgleaks the same way it is done with other sources?
Those separared Cus for computing: Wasnt that info from them?