Fox5 said:
How about a 1.5ghz 386 with 64MB L1 cache and 256MB L2 cache?
When you say 386, do you mean the actual old-timer 386 chips?
Even with the impossibly huge caches, the 386 would lose, and lose badly. A simple register to register add takes 2 cycles on a 386 (memory register adds took a minimum 7 cycles). Rudimentary pipelining could shave off a cycle if no address offsets were needed for the next instruction, meaning if the only thing you wanted to do was only repeated register adds, 1.5 billion adds a second are possible.
On an alpha EV6, even without caches that huge, something so simple as endlessly adding can be dispatched 4 times a clock cycle. So to match a 1 Ghz alpha on insanely pointless code, this 386 would have to go 4 Ghz doing only a little more than nothing.
On any code not trivially easy, the lack of pipelining would slam the single-issue 386 down to an execution rate of a fraction of an instruction per cycle. This is assuming the giant cache removes all memory considerations (it won't, especially not with the ISA exposed to a 386).
Far smaller caches have something higher than 80% of that effectiveness already, and with the die area of cache that huge, you could fit a half dozen alphas with far better effect.
A modern processor, unless you are deliberately telling it to idle, will fail miserably at cutting its execution rate anywhere near that low, and it will have floating point capability to boot.
edit: not to say that superscalar processors are all that great at getting more than 1 instruction executed per clock thanks to memory latency and other hazards. I think someone gave an average of .8 instructions per clock for a K8. If the old chips weren't orders of magnitude worse, modern chips would look much less impressive.
Until then the scoop of this discussion will keep hiting a wall.
