"What Nehalem is really about"

pjbliverpool said:
Much of the blame lies at AMD's feet for not producing a competitive archtecture though. You can't really blame a company for milking its market when that option is available (thats not to say i'm happy with the situation - i'm seriously routing for AMD here!)
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You can blame Intel for their illegal practices. It financial hurt AMD, which in turn reduces how much they can put into R&D research and other areas.
 
That HSF looks like a finger killer. Don't mess around in the computer while it's running!
 
>.>

"Oh, god, I lost my finger a few weeks ago!"

"How'd you do that, dude?"

"Uh, um... I had my PC running with the case off, and got a little too close to the CPU fan, and..."

"Wow, you fail at life."
 
I know I'd never stick my finger between the blades of a running Delta fan... Fans used in OEM consumer systems are usually fine though :p
 
Nice results. Game results are up and down, but everything else is a win. Well-threaded and bandwidth-bound scenarios show huge gains for Nehalem, even without using HT.
 
Yep, some games are still preferring the cache combo on Penryn architecture (large and fast L2), but intensive multi-threaded app's will slide more conveniently into Nehalem's sheer SMP throughput and the fact, that thread communication is now enclosed within the on-chip L3 cache.
 
Looks like Intel's native quad is a lot more impressive than AMD's. The multithreaded performance of Core i7 is a major imrovement over C2Q. But yea it does seem that these L3 caches are bad for games, with the added latency they bring.
 
Of course it is, since amd didnt expect intel to open up a can of wupass with the core2 architecture.

Amd cant hope to compete with intel untill a major redesign occurs, not just a diestrink with perhaps a few tweaks here and there.
 
I think the die-size constrains caused this rather small size of the L2 caches. Even at 512KB per core, the L2-to-L3 inclusive relationship wouldn't hurt at the present 8MB design, but the single-threaded performance would have been additionally improved.
 
Dunnington, despite it's large (and relatively latent) L3 is still FSB-limited in multi-socket config's, but that's pretty much all that can be done for this platform. It is just a nice upgrade path for the old Xeon systems.
Even with four FSB's at 1066MT/s on the i7300 NB, each one of all the 24 cores gets just 1.4GB/s of "ideal" bandwidth.
 
fellix said:
Dunnington, despite it's large (and relatively latent) L3 is still FSB-limited in multi-socket config's, but that's pretty much all that can be done for this platform. It is just a nice upgrade path for the old Xeon systems.
Even with four FSB's at 1066MT/s on the i7300 NB, each one of all the 24 cores gets just 1.4GB/s of "ideal" bandwidth.
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Ouch
 
I'm tempted to think there was an option for quad channel design somewhere down the design road but, again, real-life constrains and considerations pushed the engineers back in a middle ground.
I think, this triple-channel design is pretty balanced, for how the CPU is able to perform. ;)
 
Davros said:
why are they using 3 sticks of ddr3 with Core i7
but 2 sticks with QX9770 is i7 tripple channel ?
Click to expand...

Yes, i7 is coming in a triple-channel flavor at the top end as well as dual-channel flavors at the lower end. Combined with the integrated memory controller, it lays down theoretical bandwidth figures nearing 40Gb/sec with DDR3-1600; expecting about 30Gb/sec in real life benches.

And while you could argue that dual-channel DDR3 overclocked to 2000Mhz could get you close to that, the problem becomes the massive bottleneck between northbridge and CPU (aka, the FSB limitation.) In reality, dual channel DDR3 running at 2000Mhz couldn't get you anywhere near that, as you were entirely bottlenecked by your puny FSB speeds and latencies to something around 12-15Gb/sec.
 
In addition to my previous post, after looking this preview of Asus P6T Deluxe (read the sticker on the DIMMs), probably the triple-channel bonanza have some roots in a possible parallel access vs. clock-rate hesitation over the memory interface performance. :???:
 
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