"What Nehalem is really about"

[Scali]

right before they just turned SMT off and went to SMP.

Yes, except for that one piece of extremeness known as the Pentium XE (I believe the 840, 955 and 965 all had that).
You got SMP *and* SMT, so that was the first series of x86/x64 processors with 4 cores on a single socket, albeit logical cores.
Ah, those were the days But anyway, I digress... Carry on

 

[Thorburn]

Yes, except for that one piece of extremeness known as the Pentium XE (I believe the 840, 955 and 965 all had that).
You got SMP *and* SMT, so that was the first series of x86/x64 processors with 4 cores on a single socket, albeit logical cores.
Ah, those were the days But anyway, I digress... Carry on

Yep, 840XE, 955XE and 965XE all had hyper-threading. Have all three of them somewhere

Ran a 955XE overclocked to 4GHz in my main system, then later my media centre, was actually a pretty decent chip at the time.

 

[crystall]

Prescott also doubled the trace caches, so that there was one for each HT context, reducing trashing.

Are you sure about that? I was under the impression that the trace cache was left unchanged and there was still only one shared by the two threads.

 

[fellix]

The trace cache was kept 12K μOp's in size throughout the entire NetBurst CPU line, from the very first Willamette core to the last 65nm DC model.