DemoCoder said:Gubbi, if tiling is so cheap, why didn't ATI use *less* eDRAM, boost yields, lower costs, increase margins, and possibly even put so little that it could fit on the main R500 core?
Clearly, ATI analyzed the issue and tried to put enough to hold 640x480x4xFSAA. There must have been a reason for their decision.
10MB was probably just a sweet spot economically and performance wise.
It appears that they needed 192 ROP processors to meet their performance target (which was a given fillrate with 4x fsaa). Considering that the transistor count for the EDRAM hovers around 150 million, the ROP part of the chip is about *half* the chip (80Mbit DRAM = 80 million transistors+some line amps+repeaters)
So cutting the DRAM part from 10MB to 2MB would only cut cost modestly. But you're right, they probably considered 640x480 the sweet spot, otherwise they could have put more DRAM in.
The entire thing probably has extra ROPs+DRAM columns for rendundancy giving it yields in the high 90s with just a few percent extra die area used.
And considering that going from 1280x720x 2xfsaa to 4xfsaa results in 92-95% the performance, flushes are cheap.
Cheers
Gubbi