ERP said:The advantage of the system in R500 is consistency.
Bandwidth can never hamper fillrate, doesn't matter if your ZBuffering, Alpha Blending, AA is on or off you get 8 pixels per clock and the bandwidth is available to exactly sustain that.
DemoCoder said:ERP said:The advantage of the system in R500 is consistency.
Bandwidth can never hamper fillrate, doesn't matter if your ZBuffering, Alpha Blending, AA is on or off you get 8 pixels per clock and the bandwidth is available to exactly sustain that.
If and only if you're backbuffer fits totally in eDRAM, you aren't using render-to-texture, and you aren't using HDR. If not, you not only take a bandwidth hit from having to copy tiles around, but you take a CPU/Vertex Shader hit from needing to tile the scene, and you lose coherency with respect to texture fetches and cache, since tiling is a huge state change.
So I doubt even the R500 will reach its peak fillrate given most workloads. If they are truly set on running at 720p 2x-4xFSAA by default, then they missed their design point and should have designed enough RAM to target that resolution. Shouldn't the design point have been enough RAM for 720p FSAAx2 HDR?
DemoCoder said:If not, you not only take a bandwidth hit from having to copy tiles around,
but you take a CPU/Vertex Shader hit from needing to tile the scene
ERP said:IMO I think the original target was 640x480x4AA, until HD became a marketing bullet point, I'd also rather all the manufacturers left the decision to support HD up to the developers. Personally I think I'd rather have 3x the flops per pixel than 3x the pixels, but I don't really see myself playing games on a HDTV anytime soon (and I own 2).
DaveBaumann said:Not sure that is the case either, since AFAIK the geomtry that isn't in the current frame tile is saved.
What about rendering to textures and the like? I envisage post-processing and more advanced rendering techniques being somewhat restricted by XENOS sharing the system-wide bandwidth. Or is this just not seen as heavy-use requirement and able to be absorbed into the existing rendering pipeline?DaveBaumann said:I'm not seeing that myself - as far as I see there is no "copying tiles around"; a tile is rendered to the EDRAM, downsampled and posted to system RAM - this only happens once whether there is a full frame or in the EDRAM or multiple tiles, except in the case there is multiple tiles is just happens more times per frame.
DemoCoder said:Don't you feel that calling this buffer format "High Dynamic Range" is a little bit disingenuous?
Well then look at it this way, the CPU has to partition the tiles, which eats cycles and bandwidth.
DemoCoder said:DaveBaumann said:Not sure that is the case either, since AFAIK the geomtry that isn't in the current frame tile is saved.
Well then look at it this way, the CPU has to partition the tiles, which eats cycles and bandwidth. Either way, its a hit that you don't take if you have enough RAM to hold the whole frame.
DemoCoder said:Now Dave is saying this would have happened anyway, but it is the lack of memory that is forcing the copy in the first place.
DemoCoder said:BTW, what will you do with 3x the FLOPs per pixel? Let's say you have tripple the R500's ALUs per pipe. What would you use all that pixel shading power for? Procedural textures? Those are not going to look good. There is a limit to what the pixel shader model can do for lighting and realistically, if you want to simulate more advanced models, you need more fillrate, not just shader ops. Pixel shaders cannot communicate with one another nor compute interactions between surfaces unless they have been written and turned into a texture already.