STM Kyro3: was it never taped out?

[Ailuros]

more of them:

GigaPixel GP1/2 (free FSAA, faster than anything else when using FSAA 4x), GP3 (EMBM, 8-layer, T&L, DXT1, 80KB SRAM)

I'm not so sure GP3 was even capable of EMBM:

http://users.otenet.gr/~ailuros/gp-3.pdf

As for the "free FSAA" yeahrightsureok. It was plain Multisampling and it means as in all other cases that it's nearly fillrate and bandwidth "free" (always in a very relative sense) compared to Supersampling. Under that sense GPUs have since the dawn of R300 already "free FSAA".

GP1 wasn't capable of AF by the way, which makes Multisampling by itself a very moot point.

http://users.otenet.gr/~ailuros/gp-1.pdf

Here are the numbers 3dfx gave to the public when they bought off Gigapixel and advertised for GP1 and GP2 licensing:

Despite it being a 100MHz core from what I recall, the results aren't something to knock me out of my socks.

OAK WARP5 (Windows accelerator and Rendering Processor) - 1997, trilinear, free FSAA

Same thing for the "free FSAA" claim; in order to get close to zero performance penalty for FSAA you're either testing a case where the system is completely CPU bound or the GPU might have a very unbalanced pipeline where the concentration on AA is higher than on anything that was ever available. PowerVR's MBX also claims "FSAA4free"; of course is it nearly resource free, but it's also from what I recall 2x sample Multisampling on one axis.

Between R300 and today's GPUs if you run in a resolution where the system is CPU bound enough the performance penalty for multisampling is relatively small and as "free" as anywhere mentioned above. On today's GPUs as long as you don't exceed 1280*1024 even 4xMSAA will tax fillrate/bandwidth and memory footprint only by very small amounts.

 

[no-X]

Ailuros: GP was tiler, so Z-buffer was on-chip, as I remember. MSAA is free in the same sense as on Xenos...

 

[Ailuros]

Ailuros: GP was tiler, so Z-buffer was on-chip, as I remember. MSAA is free in the same sense as on Xenos...

Not exactly in the same sense IMHLO; GP-1 should have had for it's timeframe (I suppose) sufficient ram as a GPU and target resolutions were much smaller for back then than today. If you want 4xMSAA on Xenos for anything above 640*480 you need (from what I recall) to use some sort of "macro-tiling" in order to fit everything in the eDRAM module. The downside is that geometry needs to get re-buffered in such a case.

And again: from GP3 and onwards MSAA would have made sense due to the presence of AF. Without AF Multisampling by itself is a moot point.

 

[Xmas]

Without AF Multisampling by itself is a moot point.

I don't quite see why that should be the case.

 

[Ailuros]

I don't quite see why that should be the case.

Maybe because I got spoiled with Supersampling first and later with Multisampling+AF combinations. If I would face an either/or dilemma I'd prefer AF anyway against MSAA.

 

[tangey]

"Gigapixel....hmmm...I have a feeling they may yet have a roll to play in the fortunes of IMG when all things that must be done are done"

(said in my very best Gandalf voice)

 

[roninja]

SGX 555 for PC????

SGX 555 - now thats something Intel could do with...but they'd need to fit it into a SoC...hang on...a Soc for the PC space don't think that will catch on.....

 

[Ailuros]

SGX 555 - now thats something Intel could do with...but they'd need to fit it into a SoC...hang on...a Soc for the PC space don't think that will catch on.....

I could be completely wrong, but it's specs sound more like IGP level at best for a =/>2009 release.

 

[Blazkowicz]

SGX 555 - now thats something Intel could do with...but they'd need to fit it into a SoC...hang on...a Soc for the PC space don't think that will catch on.....

I think that will catch on. laptops, netbooks, tiny low power desktops for the power conscious (= $$$) markets and the third world.

 

[Ailuros]

I think that will catch on. laptops, netbooks, tiny low power desktops for the power conscious (= $$$) markets and the third world.

The more "power conscious" the target markets/devices, the less it makes theoretically sense to pick something like a SGX555 over a SGX545. According to Imagination's factsheet SGX is up to 20.3mm^2@65nm for which I figure they mean the 555. The SGX included in ATOM uses a much larger manufacturing process and I've no idea what Intel's process roadmap looks like for the next year. In any case even 20 square millimeters sound scary for a future SoC.

 

[RussSchultz]

Its certainly getting too big to be a checkbox feature. (Which, unfortunately, in the SoC world, 3d is becoming).

And by checkbox I mean 'it needs to be on the box, even if the customer doesn't really need it for the application to be considered for the design win'.

 

[Mariner]

To be fair to PowerVR, the SGX variants for SoC will be nothing like the area of 20.3mm^2 quoted as the size of the SGX555. I seem to remember reading somewhere that the SGX535 (which I believe is targeted at the higher-end mobile devices/MID/basic portables) would be in the region of 7mm^2. The lower-end devices (for basic mobile phones) would of course be even smaller - figures in the region of 2-3mm^2 have been quoted I believe?

I'd imagine this would make them reasonable options as a checkbox feature for most SoCs?

 

[RussSchultz]

Well, reasonability is all about proportion.

2-3mm^2 in 90 or 65?

How much do you think a mm^2 costs in yielded die?
How much do you think the royalties are?
How much do you think the 'average' SoC costs?

 

[Ailuros]

I don't even recall how much space the SGX in current ATOM variants consumes, but I recall a bigger manufacturing process than the quoted by IMG 65nm die space figures.

And by checkbox I mean 'it needs to be on the box, even if the customer doesn't really need it for the application to be considered for the design win'.

Obviously within the Series5 family there will be a range of functionalities according to target devices and die spaces. However IMHLO there's a specific point up to where an IHV can reduce functionalities w/o ending up costing more than to leave it inside.

IMO the Series5 compatibility at its peak should exceed SM4.1 quite a bit (how much no idea); going downwards to the lowest level to something like SM3.0 makes sense. For less I don't think it makes sense anymore especially in a USC.

I haven't any idea what AMD's "mini-Xenos" looks like yet, but I'd figure it follows quite a similar reasoning, as the console chip does also have programmable tesselation capabilities just like R6x0 or higher.

 

[Dave B(TotalVR)]

Well, I'm not sure what's stopping somebody throwing a load of SGX mobile cores onto one chip and receiving pre-packaged tiles to render from the arbiter chip (im inventing this chip) which is the memory/cache controller ramdac and everthing in one. That way you could arbitrarily increase your available processing power by just adding further cores (and upping your RAM speed). Would be great from a yield point of view and not too difficult because AFAIK the SGX mobile chips aren't complete and requires the cendor to impliment the logic onto their core chip - so they deal with the memory controller for example.

BTW Ailuros, AWESOME sig I rolfed a lot.

 

[Ailuros]

ROFL something like 4 SGX555 in a chip on say 45nm? No idea but Intel so far sounds pretty conservative with manufacturing processes and the SGX parts in their ATOM designs.

It sounds more like they've been throwing R&D resources into Series6 which I guess might be announced somewhere in 2009.

 

[Simon F]

Only just noticed this:

I don't recall the details but I think it was a pre-DX8-style T&L unit. That, of course, has both advantages and disadvantages.

How much of it was related to the R&D work that went into Elan ?

Elan was "fixed-function" but still flexible in what it considered was "a light" and what it did with the "lighting" results. The advantage, IMHO, was that it could do considerably more lighting calcs per clock than a programmable core of the same sort of area, but obviously didn't have the flexibility of DX8-style T&L.

 

[Davros]

the pic in the 2nd post
2x hardware cursor why ?

 

[jlippo]

the pic in the 2nd post
2x hardware cursor why ?

I certainly would love to have windows machine which would allow several concurrent users..

 

[Simon F]

the pic in the 2nd post
2x hardware cursor why ?

I don't know for certain, but I would guess it's related to having two DACs.