R520 to have 300 Million Transistors??

I define it in the way that makes sense. 8 pipes more is 16+8 more is 24. It makes more sense to view it that way than to multiply by 2 IMO that way the rate of increase is linear and not quadratic.
 
Sxotty said:
I define it in the way that makes sense. 8 pipes more is 16+8 more is 24. It makes more sense to view it that way than to multiply by 2 IMO that way the rate of increase is linear and not quadratic.

Well that's your opinion.

But relative performance increase is what most people look at when talking about new generations of gpu/vpu's.
 
pipelines aren't necessarily the only way to increase performance. remember, the NV40 is clocked quite low compared to NV3x or R4x0.
 
AlphaWolf said:
Depends how you define bigger. As a percentage 24 is only 50% more than 16.

Actually Sxotty's interpretation is generally more accurate. Performance may not double from 16->24 like it did from 8->16 but it is most definitely a similar 'jump' in architectural terms as he stated.
 
The Baron said:
pipelines aren't necessarily the only way to increase performance. remember, the NV40 is clocked quite low compared to NV3x or R4x0.

Actually, my theory is that this is why they may be looking towards more pipelines. I'm wondering if they are still somewhat low-k shy, and so rather than looking to increase performance by moving to a low-k process, move to 110nm and use a similar die area by increasing the pipelines whilst probably maintaining similar speeds.
 
trinibwoy said:
AlphaWolf said:
Depends how you define bigger. As a percentage 24 is only 50% more than 16.

Actually Sxotty's interpretation is generally more accurate. Performance may not double from 16->24 like it did from 8->16 but it is most definitely a similar 'jump' in architectural terms as he stated.

I disagree.
 
We are allowed to have different opinions though ;) so it is ok. That is just how I look at it, so now you know, and now I know though I am sure I will forget next time as will you and elucidation will be required :)
 
Personally I'd go along with Alphawolf here - remember, the 24 pipelines comment was in relation to NVIDIA and they went from 4->16 in one step, and thats a far larger "jump" not just in terms of die size, but it requires numerous different philospohies in parallelism, structure, instruction handling and despatching etc. to be thought of, designed and implemented; once that it im place, scaling to more (or less) pipelines is a much simpler task by comparison. Adding an extra 8 fragment shaders on top of an existing 16 may sound a lot, but the extra transistor requirements will still be dwarfed by whats already there.
 
I wouldn't exclude myself a possible increase in quads; I just don't have the slightest idea where the bandwidth will come from to feed the resulting fill-rates (more or less 6 GPixels/s trilinear fill-rate).
 
How much more bandwidth will they really need if it can still only output 16 pixels per clock?
 
24/32 pipeline cards... plus SLI. Yikes.

Any word on whether or not ATI be offering dual-PCIe solutions for future cards?
 
Ailuros said:
I wouldn't exclude myself a possible increase in quads; I just don't have the slightest idea where the bandwidth will come from to feed the resulting fill-rates (more or less 6 GPixels/s trilinear fill-rate).
Almost every shader takes more than one clock today. Tomorrow this trend will be even more visible. So you don't need huge bandwidth since you'll be doing shader math inside of the chip most of the time. And that's what's really important for future titles -- really fast complex shader execution, not just pure singletexturing fillrate...
 
dksuiko said:
So just admit it, TheInquirer is on many of your start-up homepages and you love them. :)
I confess: It is and I do. :D

And frankly, I don't think there's another site on the net that has the same impact on rumors throughout the PC hardware enthusiast community, so reading it is a necessity to be 'up-to-date' with the hottest gossip.

Of course, you have to know whom to trust and their fields of expertise, Charlie knows his CPUs, while I personally refuse to read anything by AMDroid Rodriguez of Van's Hardware heritage.

Anyways, back to the topic, I'm with Dave on this, I can -technically- see nVidia going 24-pipes with a move to 110nm, but wouldn't that also require a switch back to TSMC?
 
incurable said:
Anyways, back to the topic, I'm with Dave on this, I can -technically- see nVidia going 24-pipes with a move to 110nm, but wouldn't that also require a switch back to TSMC?
What switch are you talking about? They are doing NV43 at TSMC's foundries right now.
 
DegustatoR said:
incurable said:
Anyways, back to the topic, I'm with Dave on this, I can -technically- see nVidia going 24-pipes with a move to 110nm, but wouldn't that also require a switch back to TSMC?
What switch are you talking about? They are doing NV43 at TSMC's foundries right now.
Yes, you're right, I probably should've written "... but wouldn't that also require a switch of their high-end product back to TSMC?".

Basically, what I'm shooting for is whether they'd take the risk to give a 300+ million transistor design to TSMC, considering their common past (NV3x), the difference in pricing (qualified dies vs. wafers, according to rumors) and the reported lack of capacity at TSMC.

cu

incurable
 
DaveBaumann said:
Personally I'd go along with Alphawolf here - remember, the 24 pipelines comment was in relation to NVIDIA and they went from 4->16 in one step,

Yes but I was talking about ATI that is why I said 8->16. I just assumed that they would also get a part out that would be competitive. I hope you aren't implying you don't think they will have something like that out.
 
How far do you think they can push core speeds? I would think memory speeds would be limited to what the suppliers(Samsung etc.)700 Mhz DDR3 atm(I read) can supply(most probably 800Mhz DDR3 by the time the NV50/R5XX comeout). But Core speeds would be articulated by the IHV. So how high can core speeds go at 110nm/90nm with 24/32 pipes and 300 Million transistors?

US
 
I have a quick question for all you people that actually know something about engineering.

Could/ will they ever start making smaller chips like 8 pipes that they can stack into a socket. Everyone says that the reason they don't make multi GPU cards is the the PCB gets complex, but would it be possilbe in the future to make an expandable socket. The way I am thinking is that GPU's are not interchangeable like CPU's so they could make the socket much smaller and more fragile, so that under the heatsink would be 1-4 cores all nestled up snug with the packaging not bigger than the actual cores..,. the reason of course would be to reduce the %failed chips and also they wouldn't have to use them for 9500pro's x800, 6800's and so forth but could instead just meet whatever demand there was ...
 
incurable said:
Basically, what I'm shooting for is whether they'd take the risk to give a 300+ million transistor design to TSMC, considering their common past (NV3x), the difference in pricing (qualified dies vs. wafers, according to rumors) and the reported lack of capacity at TSMC.
Well, the lack of capacity should be a non-issue, since high-end products don't sell anywhere near as many as low-end products.
 
Back
Top