PSX not at 90nm?

[Deadmeat]

...

Is there any independent confirmation of their findings?

Both Sony Electronics and SCEI are silent on this issue. If it was false, you would have seen an immediate press release denying the report.

But SCEI decided to keep quite on this issue, thereby indirectly confirming that the report was true.

 

[kaching]

Re: ...

Is there any independent confirmation of their findings?

Both Sony Electronics and SCEI are silent on this issue. If it was false, you would have seen an immediate press release denying the report.

But SCEI decided to keep quite on this issue, thereby indirectly confirming that the report was true.

So, if Sony had made a statement denying the report you would then turn around and say that Sony isn't lying simply because they denied the veracity of this report? Oh, OK

And, by "independent confirmation" I meant someone OTHER than Sony or SI who could confirm the truth one way or another. Right now, we've got two companies who have written some "facts" down on paper and those "facts" contradict what the other has written.

 

[Paul]

This is all because of CELL and the 1 TFLOP broadband engine thing described in the patent. It requires a fab capability far beyond what Intel and IBM has to bring such a mystical device out. Maybe in 2010, but not in 2005.

Then again..

SCE and Toshiba have entered into a joint development
agreement (the "[*] Agreement") with [*] to develop a broadband microprocessor
(designated as the "Broadband Engine") for a [*] product;

http://library.consusgroup.com/library_pvw/147201.asp


But please, continue.

 

[nondescript]

I agree with DMGA on this one. If the report was false, they would've released a press statement denying it. (Sort of like how if a girl doesn't respond relatively quickly after asking her out, that means no.)

My guess is they're going to try to keep it low-profile, and after the 90nm chips start shipping, it will be come a non-issue. The average consumer doesn't care either way.

It makes me wonder why Sony asserted that PSX was on 90nm technology in the first place - after all, the PS2's EE and GS have been shrunk over the years with little or no fanfare - why bother talking up 90nm? Hmm.

( I would give my opinion on reverse-engineering firms like Chipworks and SI, but that would be OT)

 

[-tkf-]

Well, until a 2nd part shows up with evidence or SONY admits that they were wrong i don't consider anything proof'd.

As far as lying goes i'm pretty sure we all remember the "real time" Robot demo on the X-Box, you know the prerendered 3DMAX animation made by Blur Studios

And i'm still waiting to see the "3xtimes the power of an PS2" on my XBOX

And as far as i know Sony did similar things at the PS2 presentation without any investors calling for a lawsuit and the police.

 

[nondescript]

Never mind my last post:

http://www.eetimes.com/semi/news/OEG20040130S0027

Sony's response.

In a nutshell, Sony says that they've got 90nm, but there definitions may be slightly different (metal pitch vs gate length), and parts of the chip the (eDRAM) are fabbed at 130 nm.

 

[Deadmeat]

...

EE block = 130 nm
GS eDRAM = 130 nm
GS logic block = 90 nm???(What do you gain by redesigning the GS logic block to smaller geometry when it didn't take up too much space in the first place?)

Can you mix and match different geometry on same die???

Well, this PSX2OAC(EE+GS@90nm) is mostly a 130 nm device based on Sony's own wording. I still don't understand why SCEI deviates from industry accepted standard and calls it a 90 nm device.

The conclusion of this article..

“Nobody's been able to produce a 90-nm chip yet. I'm sure somebody will do it in 2004,â€￾ said Keyes.

PS. This PSX2OAC image is not to scale, since it appears smaller than 73 mm2 GS

 

[Deadmeat]

...

Let's do some number crunching here.

EE@130 nm = 55 mm2 <- reduced from 150 nm geomtry
GS@130 nm = 73 mm2

EE+GS@130 mm projected = 128 mm2
EE+GS@130 mm actual = 90 mm2

Difference = 38 mm2
% Difference = 30%

Did SCEI save 30% in die size by not having to include pads for GIF bus and other optimization techniques and not through geometry shrink??? Seems like that to me.

Anyhow, it IS clear that PSX2OAC is not a full 90 nm device, because you would see a die reduction to 64 mm2 or less if it were one.
Also this accounts for the transistor density difference between PSX2OAC and Intel Dothan, which has 3X transistor density of PSX2OAC.

If Sony's present "90 nm" fab is really 130 nm, then Sony's "65 nm" fab is comparable to 90 nm fab of Intel.

 

[marconelly!]

Indeed it's not a 100% 90nm chip, but sony claims most of it is, or something like that. Here's their response:

Sony quickly rejected that assessment and reiterated its contention that the EE+GS device is “fabricated in a 90-nm process as defined by the ITRS road map,â€￾ a Sony spokesman said. The single-chip EE+GS processor has never been made in a 130-nm process, not even in an engineering sample, the spokesman added.

Before merging the EE and GS processors into one, Sony fabricated the Graphics Synthesizer chip using a 130-nm process. The Emotion Engine was produced in a 150-nm process, he added.

Referring to “misunderstandingsâ€￾ in the way Semiconductor Insights measured the EE+GS processor, engineering sources at Sony acknowledged that Sony used a geometry rule “a little bit more relaxed than 90 nmâ€￾ in certain portions of the EE part of the design. Sony said the GS block was completely redesigned based on a 90-nm library. The embedded-DRAM block is one generation behind the logic, and uses a 130-nm process, according to a second Sony spokesman.

 

[chapban.]

Interesting link nondescript

Semiconductor Insights' allegation, however, sounded credible to those familiar with the chip industry's struggle to improve 90-nm yield rates. “Nobody is pushing [90-nm logic] to real volume production yet,†said Joe D'Elia, director of iSuppli Europe, a market research firm. “The closest to it is probably Intel Corp.â€

To meet the demand for chips in PSX consoles, D'Elia said that both Toshiba and Sony must have already had adequate engineering lines pumping out quite a few thousand logic chips in the 90-nm process by the middle of 2003. “That just doesn't tie up with what we see in the semiconductor industry in general,†he said.

Sony declined to comment on the production capacity and yield rate of the CMOS4 process at its Nagasaki plant. The company has said it sees an urgent need to strengthen its core consumer products by leveraging its IC technology. Katsuaki Tsurushima, electronics chief technology officer at Sony Corp., told EE Times last fall that Sony's future as a leader in the consumer industry rests upon “our own key device technologies, including semiconductors.â€

“Manufacturers, including Sony, are under great market pressure to deliver at 90 nm, but the reality is many are not ready,†said Semiconductor Insights' Nuhn. “We often see discrepancies between announced ship dates and technology nodes.â€

Keyes said he wasn't sure where the chip Semiconductor Insights analyzed had been made. The names of both Toshiba and Sony are inscribed on the die, he said. Keyes said a 130-nm transition for the EE+GS chip made sense, since the separate Emotion Engine and Graphics Synthesizer used in the Playstation had been fabricated using a mix of 0.25-micron and 0.18-micron process technologies.

“Nobody's been able to produce a 90-nm chip yet. I'm sure somebody will do it in 2004,†said Keyes.

Guess that brings into question just how sposedly (we, here, are led to believe) "bleeding edged" Sony fab capabilities are.

 

[V3]

“We took a cross-section through a dense logic area and measured the smallest gate lengths we could find and compared them with the ITRS road map,â€￾ said Edward Keyes, chief technology officer of Semiconductor Insights, referring to the International Technology Roadmap for Semiconductors. “That says an LG [gate length] of 37 nm equates to a 90-nm process. We found the smallest LG was 70 nm, which equates to a 130-nm process. The ITRS specifies an LG of 65 nm for a 130-nm process.â€￾

SI got it right, this maybe on 90nm process, but they might as well call it 130nm chip

Toshiba uses the metal pitch, not gate length, to define the 90-nm process, the spokesman said. For the 90-nm process, the L and S of metal-1 measure 240 nm, or 120 nm for each line and space, which corresponds to the 90-nm node, according to a source close to the process technology. The same source pointed out that transistor gate length varies even in the same process node. If high performance is required, the gate length is made shorter, but the geometry can be lax when less performance is required.

Ahh just as I thought, Toshiba doesn't use gate length to define their process. This sort of explain why their eDRAM cell was abit big for 65nm process.

Now my question, does TMSC or Intel define their process like this too ?

 

[asicnewbie]

Re: ...

EE block = 130 nm
GS eDRAM = 130 nm
GS logic block = 90 nm???(What do you gain by redesigning the GS logic block to smaller geometry when it didn't take up too much space in the first place?)

To help Sony's fabs gain experience-points with 90nm process-tech? Process-migration (of a part) is certain easier when the part's functionality is known and proven in an older process. Intel's first 0.13u CPUs to become available were the mobile Pentium3 and desktop/server Pentium3 (Tualatin.)

Can you mix and match different geometry on same die???

Yes. Nothing prevents a designer from putting larger-than-minimum transistor-structures on a die. Naturally, you'd expect someone to exercise a given process-node (90nm in this case) to its fullest. My guess is that Sony's e-DRAM process wasn't ready in time for their production deadline, so they switched to a more conservative 130nm e-DRAM cell-size (while continuing to refine 90nm in their development fabs.)

More generally, some companies have mixed process-nodes on a single wafer. Xilinx fabbed its Spartan2 using 0.25u for the transistor-logic, and 0.22u for the metal interconnect (and I think Trident Microsystems did the same for its Blade3D VGA.)

Well, this PSX2OAC(EE+GS@90nm) is mostly a 130 nm device based on Sony's own wording. I still don't understand why SCEI deviates from industry accepted standard and calls it a 90 nm device.

Strictly speaking, Sony didn't deviate from ITRS guidelines, as the guidelines refer to production-process and not the product itself. If any portion of the product contains 90nm transistor features, that's enough to validate the 90nm fabrication-line. 130nm equipment certainlly could not produce the chips in question, at any commercially usable yield-rate.

The fact that Sony's product (EE+GS@90nm), contains an unusually large portion lower-density logic, calls into question Sony's 90nm production-readiness.

This reminds me of Intel's "Coppermine" (0.18u Pentium3.) Intel introduced copper-interconnect (metal) at the 0.18u node. Most of the Coppermine's metal-layers used conventional (aluminum.) Only the top (highest) metal-layers used copper. Copper offers lower resistance and hence better performance than aluminum, but suffered from early production problems (due to its brittleness.)

“Nobody's been able to produce a 90-nm chip yet. I'm sure somebody will do it in 2004,â€￾ said Keyes.

Keyes' statement is rather sloppy for an 'industry expert.' It really should read "Nobody's been able to ship production-quality 90nm logic chips yet." Xilinx has been shipping engineering-samples of its 90nm Spartan3 FPGAs for 3 quarters (9 months) now. And obviously, Intel has been struggling with the Prescott's retail release. (Early engineering samples have been floating around for at least 6 months now.)

 

[Panajev2001a]

Indeed it's not a 100% 90nm chip, but sony claims most of it is, or something like that. Here's their response:

Sony quickly rejected that assessment and reiterated its contention that the EE+GS device is “fabricated in a 90-nm process as defined by the ITRS road map,â€￾ a Sony spokesman said. The single-chip EE+GS processor has never been made in a 130-nm process, not even in an engineering sample, the spokesman added.

Before merging the EE and GS processors into one, Sony fabricated the Graphics Synthesizer chip using a 130-nm process. The Emotion Engine was produced in a 150-nm process, he added.

Referring to “misunderstandingsâ€￾ in the way Semiconductor Insights measured the EE+GS processor, engineering sources at Sony acknowledged that Sony used a geometry rule “a little bit more relaxed than 90 nmâ€￾ in certain portions of the EE part of the design. Sony said the GS block was completely redesigned based on a 90-nm library. The embedded-DRAM block is one generation behind the logic, and uses a 130-nm process, according to a second Sony spokesman.

The e-DRAM block was one generation behind the logic ?

Did they also implemented the ASC9 trench capacitor e-DRAM in 130 nm or is this stacked capacitor e-DRAM ( the one co-developed with Fujitsu ) ?

Maybe their current CMOS4 process, as used in the EE+GS@90 nm early production, did not have the 90 nm ASC9 e-DRAM implemented yet.. they might be really pad limited still and did not feel the need of rushing in 90 nm e-DRAM.

Ahh just as I thought, Toshiba doesn't use gate length to define their process. This sort of explain why their eDRAM cell was abit big for 65nm process.

Now my question, does TMSC or Intel define their process like this too ?

Let me see if I can answer with an example.

Intel's 65 nm SRAM cell: 0.57 um^2.

CMOS5 ( 65 nm process by Sony and Toshiba )'s SRAM cell: 0.6 um^2.

Not too shabby considering that at Intel you have perhaps the best SRAM designers in the world.

 

[V3]

Let me see if I can answer with an example.

Intel's 65 nm SRAM cell: 0.57 um^2.

CMOS5 ( 65 nm process by Sony and Toshiba )'s SRAM cell: 0.6 um^2.

Not too shabby considering that at Intel you have perhaps the best SRAM designers in the world.

Not too mentioned Intel SRAM is faster too. But I was referring to eDRAM cell though.

But lets not get side track here.

The e-DRAM block was one generation behind the logic ?

Did they also implemented the ASC9 trench capacitor e-DRAM in 130 nm or is this stacked capacitor e-DRAM ( the one co-developed with Fujitsu ) ?

Maybe their current CMOS4 process, as used in the EE+GS@90 nm early production, did not have the 90 nm ASC9 e-DRAM implemented yet.. they might be really pad limited still and did not feel the need of rushing in 90 nm e-DRAM.

Remember according to the SI report these eDRAM cell were trench capacitor.

As for pad limited or not, I wouldn't be suprised if they shrunk this chip some more.

 

[Vince]

This sort of explain why their eDRAM cell was abit big for 65nm process.

Actually, you've posted this type of comment on multiple occasions without any basis or comperable cell sizes. Care to do this now? Would be interesting to see, Thanks.

 

[Panajev2001a]

Let me see if I can answer with an example.

Intel's 65 nm SRAM cell: 0.57 um^2.

CMOS5 ( 65 nm process by Sony and Toshiba )'s SRAM cell: 0.6 um^2.

Not too shabby considering that at Intel you have perhaps the best SRAM designers in the world.

Not too mentioned Intel SRAM is faster too. But I was referring to eDRAM cell though.

But lets not get side track here.

Well, NEC's 65 nm e-DRAM cells are 33% bigger than what Sony and Toshiba achieve with their 65 nm manufacturing process ( 0.11um^2 ) IIRC.

 

[akira888]

Well, NEC's 65 nm e-DRAM cells are 33% bigger than what Sony and Toshiba achieve with their 65 nm manufacturing process ( 0.11um^2 ) IIRC.

According to EETimes STI's eDRAM has a density of 900Megabits/cm^2, so your number is correct if EETimes is. What's odd is that I remember reading about much higher densities for 65nm litho eDRAM, maybe it was Sony, 1600Mbits/cm^2 or thereabouts...

 

[Panajev2001a]

http://www.toshiba.co.jp/about/press/2002_12/pr0301.htm

2) Embedded DRAM cell:
High-speed data processing requires a single-chip solution integrating a microprocessor and embedded large volume memory. Toshiba is the only semiconductor vendor able to offer commercial trench-capacitor DRAM technology for 90nm-generation DRAM-embedded System LSI. Toshiba and Sony have utilized 65nm process to technology to fabricate an embedded DRAM with a cell size of 0.11um2, the world's smallest, which will allow DRAM with a capacity of more than 256Mbit to be integrated on a single chip.

I do only remember Intel beating Sony and Toshiba, but that was in regard to the SRAM cell's size.

 

[V3]

Actually, you've posted this type of comment on multiple occasions without any basis or comperable cell sizes. Care to do this now? Would be interesting to see, Thanks.

Sure.

http://public.itrs.net

I can't seems to find the 1999 Roadmap but that IBM article that has the summary of the roadmap can be still be found here.

http://researchweb.watson.ibm.com/journal/rd/462/nair.html

On the other hand, at 4 Gb/cm2 one could put 11 Gb of DRAM in the same area, assuming that the DRAM-with-logic technology matures as expected.

And to safe everyone trouble I'll put up part of the table that SI uses to determine EE+GS.

Part of Table 47a High-performance Logic Technology Requirements—Near-term from ITRS 2003

Year of Production             2003  2004  
Technology Node                      hp90
DRAM ½ Pitch (nm)               100   90
MPU/ASIC(M1)½Pitch(nm)         120    107   
MPU/ASIC ½ Pitch (nm)          107    90  
MPU PrintedGateLength(nm)       65    53    
MPU PhysicalGateLength(nm)     45     37  
Physicalgatelength(HP)(nm)      45    37

This table hard to format

Anyway From that table 90nm process has physical gate of 37nm as the SI claimed. However Sony or Toshiba identify their process by Metal Pitch, and not Gate length, that's where to confusion arise. Normally gate length is also associated with process in high performance devices, like say Intel's Pentium chips.

and to keep Vince from lashing out at me all the time,

Part of Table 73a DRAM Trench Capacitor Technology Requirements—Near-term from ITRS 2003.

Year of Production          2003  2004  2005  2006  2007 2008  2009
Technology Node                   hp90               hp65
DRAM ½ Pitch (nm)           100     90    80    70   65    57    50
DRAM Product                 1G    1G     2G    2G    2G    4G    4G
Cell size factor             8     8      8      8     8      8      8
Cell size (µm 2 )            0.08 0.065 0.051 0.039 0.034 0.029 0.02

Hope those code work.

 

[Panajev2001a]

Normally gate length is also associated with process in high performance devices, like say Intel's Pentium chips.

Are you saying that prescott has 90 nm for its physical gate length ? ( prescott is Intel's first 90 nm chip and IIRC Intel said that the gate length for it was quite less than 90 nm ).

You are saying that for Toshiba and Sony when they say 90 nm, 65 nm and 45 nm they mean Metal Pitch, but this seems the case with Intel too judging Prescott.



I do not understand how supposely the world's smallest ( uncontested ) e-DRAM using 65 nm technology is quite bigger than what you have for the 100 nm node.