Semi Insights stands by 'not 90-nm' description of PSX chip
By Peter Clarke
Silicon Strategies
02/05/2004, 12:11 PM ET
LONDON -- Canadian technology and patent analysis company Semiconductor Insights re-iterated its claim that the manufacturing process used to implement the processor used within Sony's Playstation X entertainment system, was not a 90-nm process, on Thursday (February 5, 2004).
This was despite Chipworks Inc, a rival Canadian engineering consultancy, claiming it had found transistors with physical gate lengths considerably smaller than those found by Semiconductor Insights and indicative of a leading-edge process. And despite Sony insisting its Emotion Engine and Graphics Synthesizer, or EE+GS, processor was being built on a 90-nm manufacturing process, as it had always claimed.
The previous week Kanata, Ontario-based Semiconductor Insights had said the smallest physical gate lengths it had found, after sampling multiple sites on the chip, were of 70-nm, and that this was slightly larger than the 65-nm the International Technology Roadmap for Semiconductors (ITRS) equates to a 130-nm manufacturing process.
This, together with a metal-one pitch that Semiconductor Insights measured as being closer to the ITRS 2003 definition for a 130-nm process than a 90-nm process, and similarly relaxed embedded DRAM measurements, had persuaded the firm to go public with its claim (see story).
At the time Edward Keyes Semiconductor Insights chief technology officer said: "It's clear that it's a 130-nm chip, not a 90-nm chip, as defined by the ITRS,"
But on Wednesday (February 4, 2003) Ottawa-based Chipworks published a photograph on its website identified as showing a cross-section of deep-submicron transistors within a CXD9797GB, the official part number of EE+GS processor. Transistors are marked as having physical gate lengths of 46.7-nanometers and 47.5-nanometers.
Although Chipworks acknowledged these did not meet the ITRS 2003 definition for a 90-nm process, the engineering firm observed that the 90-nm manufacturing process from Intel Corp. is reported to have a gate length of 45-nm, barely different from the smallest gate lengths found in the Sony PSX processor.
When asked by Silicon Strategies on Wednesday (February 4, 2004) if Semiconductor Insights could have missed some more aggressively scaled transistors in its original measurements, Edward Keyes, chief technology officer of Semiconductor Insights said that Sony has never claimed to have such small geometry 47-nm transistor gate lengths in its 90-nm process.
Sony's published gate length claims for the CMOS4 process and the ASC9 embedded DRAM process match Semi Insights' findings of 70-nm, Keyes said. Semi Insights has confirmed those measurements and pointed that is not a 90-nm process by the ITRS tables, Keyes added.
Keyes acknowledged it is not possible to measure every transistor but also said it is not necessary as transistors don't come in an infinite number of sizes.
"Engineers don't have the freedom to alter the gate length," said Keyes.
Silicon Strategies asked if it was possible that different logical gates, such as different versions of NAND, with different fan-outs or with different drive strengths, selectable from a library, might result in transistors which when finally etched and diffused in silicon have different physical gate lengths.
"If half of one percent of the gates are at some extreme point does that make the chip belong to the next process node? I would say no," Keyes said in answer.
Reasons why measurements may differ
Keyes said he was reluctant to comment on the Chipworks scanning electron microscope photograph as he did not know how the microscope had been set-up to take the photograph. "There are a couple of reasons you might get different measurements though."
Keyes said that typically gate polysilicon is etched back in preparing the sample. This produces sharp edges that will emit electrons strongly. This can make the surrounding buffer oxides appear thicker than they really are and make the gate appear shorter.
The second possibility is the geometrical effect of taking an end-of-gate slice rather than going through the middle of the transistor when cross-sectioning the chip.
Rather like slicing though the edge, rather than the middle of an orange this has the effect of making the polysilicon gate (the flesh of the orange) look narrower and the oxides (the pith) appear wider.
When asked how it was possible to now whether a sliced transistor was a good representation of the gate length or an end-of-gate aberration Keyes said, "It comes down to the law of averages. If 99 percent are the transistors are constant and there's a few 30 percent smaller you discount it."
Keyes acknowledged that he would expect end-of-gate slices to vary and not to show identical reduced measurements.
Keyes added that Semiconductor Insights assessment had not just rested on the lack of sub-70-nm gate length transistors but also on the metal-one pitch which had measured at 260-nm. Keyes said the ITRS definition gives 210-nm for a 90-nm manufacturing process and 295-nm for a 130-nm process.
Dick James, senior technology analyst for Chipworks, said he could not identify whereabouts in the EE+GS processor sub-50-nm transistors had been found, because, until an example chip is delayered, the transistor layout remains hidden under upper metal layers.
James said he also believed that the transistors Chipworks had found were not end-of-transistor anomalies because several transistors in a line had produced similar measurements in each transistor. If an end-of-transistor anomaly was being measured you would expect the measurements to vary, he said, unless the cut happened to hit the arc of each transistor-end in the same place.
James also said that Chipworks was familiar with edge-effects in samples prepared for scanning electron microscopy by etching. "There is a bit of distortion depending on beam energy. But when you're looking at a gap like this I've got more confidence. Our SEMs are calibrated to within plus or minus 5 percent," said James.
"We did see wider polysilicon lines. But we see p-channel at 48 to 49-nm and n-channel transistors at 46 to 47-nm. The embedded DRAM is more relaxed but you'd expect that."
After studying Chipworks' photograph Semiconductor Insights' Keyes wrote an email to Silicon Strategies saying: "It's apparent that the line-end effect that we talked about is not occurring in this cross-section and hence cannot be the explanation for their smaller measurement. We do still stand by our original statement that this is not 90-nm technology according to the roadmap and we will be investigating further."
