PSX not at 90nm?

[chapban.]

From the-magicbox.com....

Sony has denied the report about the EE+GS processor in PSX is manufactured in 130nm technology, Sony stated the final manufacturing process is done with 90nm technology

old...
This "denial" has been posted in this topic IIRC... denied more due to how quirky Sony defined their 90nm process.

 

[Johnny Awesome]

Sony = Pants down. Even Vince can't seem to pull them back up.

 

[cthellis42]

Yeah, the EETimes article does a good sum-up job. Sony/Toshiba go by metal pitch (and need 90nm equipment to bring it about), and SI seemed to only be measuring gate length (and likely we'll never know more about that, since no one around here is going to pay $1000 to get the full report--heh...)

I'm not sure how people are so flat-footed by it, though--in fact, didn't we have a discussion on just that matter a while back? (It might be somewhere else I'm thinking of.) As DM mentioned, a proportional shrink of a 73mm² EE at 150nm and of a 73mm² GS at 130nm to 90nm both (all else being equal) ends up somewhere in the 60's, which is notably below the 86mm² announced. And the proposed 86mm² (90mm² in actuality) would in turn be sizably below an EE+GS that only had the EE shrunk to 130nm. So what do you have? Well, it doesn't become a 110nm chip by being between two standards...

The structure of the EE+GS is peculiar, but so is the nature of it. It doesn't have to offer an ounce more performance than the chips did in 1999 (in fact, they may end up causing problems if they did so), it's not on a strict release schedule, and there are no products depending on it to exist and compete directly with other chip architectures. In other words, it can concentrate solely on monetary concerns, because that's basically what it is--a cost-cutting chip for devices they know they're going to sell millions more of, and if they get low enough may replace others or get adopted in new products as well. When will the DRAM shrink? When it doesn't affect yields too much and counteract the material savings. When will gate length shrink? WILL it; does it need to? There are boons to reducing leakage for a product like this, to be sure, and there's no incentive to take any steps involved in pushing more performance through it, so...? (What other advantages would wider gates bring? Are there discernable monetary impacts?)

Does it point to problems they're having with 90nm? <shrugs> No idea. Will it translate to problems at 65nm? I dunno... Will Intel's? AMD's? Will IBM's overall successes at 90nm automatically translate to the same at 65nm? Do yield problems and delays at 130nm for one chip translate to the same for another, even at the same fab? At this point, I've come to think that high-end tech just moves way too fast and weirdly to be accurately predicted. "Track record" only goes so far, and we ALWAYS see too little to really know what's going on. "We'll see what it's like when it's here" seems to be the only rule at this point, and though it's fun to speculate--it goes relatively nowhere. Previous to R300, who would have predicted that result from ATi? Who would have predicted NV30's handling from nVidia? Who was expecting Prescott to be continually delayed and look like it does now? Flip-flops happen all too easily, and the console industry has certainly shown THAT, too.

For those of us tracking the tech for tech's sake, though, there is indeed plenty of "creative misdirection" and "assumption by exclusion" in this case, and sadly it's rather rampant across the tech industry, whether one's name is Sony, Intel, AMD, nVidia, ATi, Microsoft, Apple... Every company keeps their tech specifics as much under lock-and-key as possible, every company puts their best feet forward whether it is ignoring the entire context or not, and no company likes it to be known when they have to backslide or make sacrifices one way or another. I'd much rather there be a lot more transparency on the tech specifics companies are using... but then again, so are their rivals. I certainly don't "forgive" any of them for their examples of it, but I fear the situation will only worsen over time. :?

 

[Vince]

Sony = Pants down. Even Vince can't seem to pull them back up.

I'd assume this is indicative of your level of understanding of this topic. Perhaps you should read Cthellis's post, which is good, that follows your enlightened comment, before posting.

I'd assume the fact that Sony has a 90mm2 integrated IC that's obviously not 130nm and roughly inline with their 90nm projections, while the competition is utilizing two ICs of significant size and cost, would mean that they were never really down.

 

[nobie]

Fabs refine their technology all the time....a mature 90nm process may be more like 80nm, and an immature process may be more like 100nm, that's not uncommon.

 

[MfA]

Their rivals know most things worth knowing about the chip the moment it hits the street ... it's only us who are left in the dark.

 

[cthellis42]

Hrm... Probably a good point. Nothing stopping them from buying chips and looking at it under an electron-microscope, either. (They just have to figure how to implement features around patents.)

I guess maybe they just don't want the press and public at large able to go into anything much?

 

[Panajev2001a]

Yeah, the EETimes article does a good sum-up job. Sony/Toshiba go by metal pitch (and need 90nm equipment to bring it about), and SI seemed to only be measuring gate length (and likely we'll never know more about that, since no one around here is going to pay $1000 to get the full report--heh...)

I'm not sure how people are so flat-footed by it, though--in fact, didn't we have a discussion on just that matter a while back? (It might be somewhere else I'm thinking of.) As DM mentioned, a proportional shrink of a 73mm² EE at 150nm and of a 73mm² GS at 130nm to 90nm both (all else being equal) ends up somewhere in the 60's, which is notably below the 86mm² announced. And the proposed 86mm² (90mm² in actuality) would in turn be sizably below an EE+GS that only had the EE shrunk to 130nm. So what do you have? Well, it doesn't become a 110nm chip by being between two standards...

The structure of the EE+GS is peculiar, but so is the nature of it. It doesn't have to offer an ounce more performance than the chips did in 1999 (in fact, they may end up causing problems if they did so), it's not on a strict release schedule, and there are no products depending on it to exist and compete directly with other chip architectures. In other words, it can concentrate solely on monetary concerns, because that's basically what it is--a cost-cutting chip for devices they know they're going to sell millions more of, and if they get low enough may replace others or get adopted in new products as well. When will the DRAM shrink? When it doesn't affect yields too much and counteract the material savings. When will gate length shrink? WILL it; does it need to? There are boons to reducing leakage for a product like this, to be sure, and there's no incentive to take any steps involved in pushing more performance through it, so...? (What other advantages would wider gates bring? Are there discernable monetary impacts?)

Does it point to problems they're having with 90nm? <shrugs> No idea. Will it translate to problems at 65nm? I dunno... Will Intel's? AMD's? Will IBM's overall successes at 90nm automatically translate to the same at 65nm? Do yield problems and delays at 130nm for one chip translate to the same for another, even at the same fab? At this point, I've come to think that high-end tech just moves way too fast and weirdly to be accurately predicted. "Track record" only goes so far, and we ALWAYS see too little to really know what's going on. "We'll see what it's like when it's here" seems to be the only rule at this point, and though it's fun to speculate--it goes relatively nowhere. Previous to R300, who would have predicted that result from ATi? Who would have predicted NV30's handling from nVidia? Who was expecting Prescott to be continually delayed and look like it does now? Flip-flops happen all too easily, and the console industry has certainly shown THAT, too.

For those of us tracking the tech for tech's sake, though, there is indeed plenty of "creative misdirection" and "assumption by exclusion" in this case, and sadly it's rather rampant across the tech industry, whether one's name is Sony, Intel, AMD, nVidia, ATi, Microsoft, Apple... Every company keeps their tech specifics as much under lock-and-key as possible, every company puts their best feet forward whether it is ignoring the entire context or not, and no company likes it to be known when they have to backslide or make sacrifices one way or another. I'd much rather there be a lot more transparency on the tech specifics companies are using... but then again, so are their rivals. I certainly don't "forgive" any of them for their examples of it, but I fear the situation will only worsen over time. :?

*Standing Ovation*

 

[nondescript]

The structure of the EE+GS is peculiar, but so is the nature of it. It doesn't have to offer an ounce more performance than the chips did in 1999 (in fact, they may end up causing problems if they did so), it's not on a strict release schedule, and there are no products depending on it to exist and compete directly with other chip architectures. In other words, it can concentrate solely on monetary concerns, because that's basically what it is--a cost-cutting chip for devices they know they're going to sell millions more of, and if they get low enough may replace others or get adopted in new products as well. When will the DRAM shrink? When it doesn't affect yields too much and counteract the material savings. When will gate length shrink? WILL it; does it need to? There are boons to reducing leakage for a product like this, to be sure, and there's no incentive to take any steps involved in pushing more performance through it, so...? (What other advantages would wider gates bring? Are there discernable monetary impacts?)

Does it point to problems they're having with 90nm? <shrugs> No idea. Will it translate to problems at 65nm? I dunno... Will Intel's? AMD's? Will IBM's overall successes at 90nm automatically translate to the same at 65nm? Do yield problems and delays at 130nm for one chip translate to the same for another, even at the same fab?

Nail on the head. Why waste money?

Let's all wait for PSP.

 

[cthellis42]

They have to save up to be able to waste a lot more money on PS3, after all.

 

[V3]

Does it point to problems they're having with 90nm? <shrugs> No idea. Will it translate to problems at 65nm? I dunno...

Before the SI investigation, how was the EE+GS@90nm info use on this board ? Its use to claim Sony is on track with their processes, now we dunno ?

 

[Deadmeat]

...

Before the SI investigation, how was the EE+GS@90nm info use on this board ? Its use to claim Sony is on track with their processes, now we dunno ?

Well, Sony's process has been always kind of fishy. I kept pointing out the fact that Intel's 90 nm processor had 3X the transistor density of supposedly "90 nm" PSX2OAC, but nobody listened....

 

[Joe DeFuria]

Actually, it seemed to me that quite a few people around here "cared" that Sony fas fabbing "90nm" chips...

 

[kaching]

Does it point to problems they're having with 90nm? <shrugs> No idea. Will it translate to problems at 65nm? I dunno...

Before the SI investigation, how was the EE+GS@90nm info use on this board ? Its use to claim Sony is on track with their processes, now we dunno ?

Well, nobody here ever did know...from what I can tell you're all just on the outside looking in, speculating wildly based on the glimpses you catch. Somewhere along the way, some have lost sight of the fact that this all just speculation, on BOTH sides.

 

[London Geezer]

Actually, it seemed to me that quite a few people around here "cared" that Sony fas fabbing "90nm" chips...

1) It was a joke.
2) If it were to be taken seriously, it was referred to "the fact that Intel's 90 nm processor had 3X the transistor density of supposedly "90 nm" PSX2OAC, but nobody listened...." comment Deadmeat did, not "That Sony was fabbing 90nm chips".
3) It was a joke.

 

[Johnny Awesome]

Spin it however you want Vince, but Sony is behind where you indicated they were in the lithography race that you say is so critical. So that means your pants are down too.

 

[Vince]

Spin it however you want Vince, but Sony is behind where you indicated they were in the lithography race that you say is so critical. So that means your pants are down too.

Hardly, Toshiba has been shipping 90nm SoC's for months aswell. The technology is sound and in mass production, within 6-9 months Sony and Toshiba will have more 90nm ICs out there than XBox's over the past 3 years.

They're CMOS 90nm process is capable of 45nm gate lengths, and within a year we'll see STI's 65nm test chips. Behind is hardly the case. But, I reckon you'll never understand the diffence between a process technology and an implimentation.

 

[gurgi]

But, I reckon you'll never understand the diffence between a process technology and an implimentation.

I'm not sure investors will either. As a manufacturer, it takes implimentation to generate profits.

 

[Panajev2001a]

But, I reckon you'll never understand the diffence between a process technology and an implimentation.

I'm not sure investors will either. As a manufacturer, it takes implimentation to generate profits.

If the EE+GS@90 nm the way it was implemented ends up being the most cost effective solution compared to a full 90 nm implementation ( power consumption is a factor ) then who has to worry ?

 

[Deadmeat]

...

Chipworks: PSX Chip Is Too 90nm

Online Staff -- Electronic News, 2/4/2004

Technical services company Chipworks Inc. said today that Sony's Playstation X processor was manufactured with 45nm gates, leading it to believe that it is indeed made with a 90nm process.

Another chip market research company, Silicon Insights, claimed that Sony's EmotionEngine and Graphics Synthesizer chip, found in its latest Playstation game console and which Sony says is built on a 90nm process, was actually built with a 0.13-micron, or 130nm process technology. Silicon Insights said it removed the chip from a PSX model DESR-5000, and determined it was built on 130nm technology with a die size of 90mm square.

But Chipworks announced on its site today that after reverse engineering the EmotionEngine chip, that the device has gate lengths more consistent with a 90nm process. Chipworks even has a cross section SEM image on its site of what it says are the gates of the Sony chip in question.

"Chipworks obtained a sample of the Sony PSX chip and had started to take it apart based on the reports that it was a 90nm part, but we have come to somewhat different conclusions than those reported last week," Dick James, Chipworks' senior technology analyst, said in a statement on the company's Web site. "For one thing, we found transistors with a physical gate length of 45nm to 50 nm, which immediately led us to believe that we did have a 90 nm part."

Chipworks conceded that the Sony chip, fabricated in partnership with Toshiba, while perhaps not meeting the exact definition of a 90nm process as spelled out in the International Technology Roadmap for Semiconductors, is nevertheless comparable with the leading edge Intel Corp. process in terms of gate dimension. Intel 90nm chips, as announced at last autumn's Intel Developer Forum, reportedly have gate lengths of 45nm, slightly larger that the 37nm polysilicon gate length considered the benchmark by the ITRS for the 90nm node.

The EmotionEngine chip also utilizes an advanced two stack low-k dielectric structure, according to Chipworks. This, combined with the 45nm gates, makes the chips one of the most advanced in production today, the company maintains.

Chipworks observed that the ATI RADEON 9600XT graphics processor, built by foundry Taiwan Semiconductor Manufacturing Co., like the Sony chip uses Applied Materials' Black Diamond low-k intermetal dielectrics, but with 85nm gates. This indicates it is clearly a 0.13-micron device, according to Chipworks.

Semi Insights stands by 'not 90-nm' description of PSX chip
By Peter Clarke
Silicon Strategies
02/05/2004, 12:11 PM ET

LONDON -- Canadian technology and patent analysis company Semiconductor Insights re-iterated its claim that the manufacturing process used to implement the processor used within Sony's Playstation X entertainment system, was not a 90-nm process, on Thursday (February 5, 2004).

This was despite Chipworks Inc, a rival Canadian engineering consultancy, claiming it had found transistors with physical gate lengths considerably smaller than those found by Semiconductor Insights and indicative of a leading-edge process. And despite Sony insisting its Emotion Engine and Graphics Synthesizer, or EE+GS, processor was being built on a 90-nm manufacturing process, as it had always claimed.

The previous week Kanata, Ontario-based Semiconductor Insights had said the smallest physical gate lengths it had found, after sampling multiple sites on the chip, were of 70-nm, and that this was slightly larger than the 65-nm the International Technology Roadmap for Semiconductors (ITRS) equates to a 130-nm manufacturing process.

This, together with a metal-one pitch that Semiconductor Insights measured as being closer to the ITRS 2003 definition for a 130-nm process than a 90-nm process, and similarly relaxed embedded DRAM measurements, had persuaded the firm to go public with its claim (see story).

At the time Edward Keyes Semiconductor Insights chief technology officer said: "It's clear that it's a 130-nm chip, not a 90-nm chip, as defined by the ITRS,"

But on Wednesday (February 4, 2003) Ottawa-based Chipworks published a photograph on its website identified as showing a cross-section of deep-submicron transistors within a CXD9797GB, the official part number of EE+GS processor. Transistors are marked as having physical gate lengths of 46.7-nanometers and 47.5-nanometers.

Although Chipworks acknowledged these did not meet the ITRS 2003 definition for a 90-nm process, the engineering firm observed that the 90-nm manufacturing process from Intel Corp. is reported to have a gate length of 45-nm, barely different from the smallest gate lengths found in the Sony PSX processor.

When asked by Silicon Strategies on Wednesday (February 4, 2004) if Semiconductor Insights could have missed some more aggressively scaled transistors in its original measurements, Edward Keyes, chief technology officer of Semiconductor Insights said that Sony has never claimed to have such small geometry 47-nm transistor gate lengths in its 90-nm process.

Sony's published gate length claims for the CMOS4 process and the ASC9 embedded DRAM process match Semi Insights' findings of 70-nm, Keyes said. Semi Insights has confirmed those measurements and pointed that is not a 90-nm process by the ITRS tables, Keyes added.

Keyes acknowledged it is not possible to measure every transistor but also said it is not necessary as transistors don't come in an infinite number of sizes.

"Engineers don't have the freedom to alter the gate length," said Keyes.

Silicon Strategies asked if it was possible that different logical gates, such as different versions of NAND, with different fan-outs or with different drive strengths, selectable from a library, might result in transistors which when finally etched and diffused in silicon have different physical gate lengths.

"If half of one percent of the gates are at some extreme point does that make the chip belong to the next process node? I would say no," Keyes said in answer.

Reasons why measurements may differ

Keyes said he was reluctant to comment on the Chipworks scanning electron microscope photograph as he did not know how the microscope had been set-up to take the photograph. "There are a couple of reasons you might get different measurements though."

Keyes said that typically gate polysilicon is etched back in preparing the sample. This produces sharp edges that will emit electrons strongly. This can make the surrounding buffer oxides appear thicker than they really are and make the gate appear shorter.

The second possibility is the geometrical effect of taking an end-of-gate slice rather than going through the middle of the transistor when cross-sectioning the chip.

Rather like slicing though the edge, rather than the middle of an orange this has the effect of making the polysilicon gate (the flesh of the orange) look narrower and the oxides (the pith) appear wider.

When asked how it was possible to now whether a sliced transistor was a good representation of the gate length or an end-of-gate aberration Keyes said, "It comes down to the law of averages. If 99 percent are the transistors are constant and there's a few 30 percent smaller you discount it."

Keyes acknowledged that he would expect end-of-gate slices to vary and not to show identical reduced measurements.

Keyes added that Semiconductor Insights assessment had not just rested on the lack of sub-70-nm gate length transistors but also on the metal-one pitch which had measured at 260-nm. Keyes said the ITRS definition gives 210-nm for a 90-nm manufacturing process and 295-nm for a 130-nm process.

Dick James, senior technology analyst for Chipworks, said he could not identify whereabouts in the EE+GS processor sub-50-nm transistors had been found, because, until an example chip is delayered, the transistor layout remains hidden under upper metal layers.

James said he also believed that the transistors Chipworks had found were not end-of-transistor anomalies because several transistors in a line had produced similar measurements in each transistor. If an end-of-transistor anomaly was being measured you would expect the measurements to vary, he said, unless the cut happened to hit the arc of each transistor-end in the same place.

James also said that Chipworks was familiar with edge-effects in samples prepared for scanning electron microscopy by etching. "There is a bit of distortion depending on beam energy. But when you're looking at a gap like this I've got more confidence. Our SEMs are calibrated to within plus or minus 5 percent," said James.

"We did see wider polysilicon lines. But we see p-channel at 48 to 49-nm and n-channel transistors at 46 to 47-nm. The embedded DRAM is more relaxed but you'd expect that."

After studying Chipworks' photograph Semiconductor Insights' Keyes wrote an email to Silicon Strategies saying: "It's apparent that the line-end effect that we talked about is not occurring in this cross-section and hence cannot be the explanation for their smaller measurement. We do still stand by our original statement that this is not 90-nm technology according to the roadmap and we will be investigating further."

SI Vs Chipworks, who's right???

Doesn't matter, PSX2OAC is still not a true 90 nm, that much is agreed upon.