PSX not at 90nm?

[Dio]

Good point... I seriously do not know how they could fit both EE and GS with 130 nm technology: the EE was 73 mm^2 in 150 nm technology and the GS in its 6th revision was 73 mm^2 in 130 nm technology.

Is it possible that the earlier designs were pad limited?

 

[V3]

Since when is this a factual news article? It's a press release, a rather specious way to present findings like this. Considering that SI is essentially claiming to have caught Sony in a lie about a product shipping to consumers why is there no indication that they've tried contacting Sony about this and why must we pay $1000 to see whether their findings are in fact accurate?

Seems more like opportunistic appropriation of permissive press release services for cheap marketing on SI's part, more than anything else.

If they're not accurate and just lie, Sony can sue them for damages. I don't think they're that naive, unless they can backup their claimed.

 

[V3]

Is it possible that the earlier designs were pad limited?

Yes, its possible, since they pretty much stop at 73 mm2. So below that point they're probably pad limited, that's probably why even at 90nm process they still hover at 86 mm2.

 

[Panajev2001a]

For $1000 you can have the full report

Sony claims to manufacture at 90 nm, but the design rules are relaxed to 130 nm. The e-DRAM trench cells are also laid out using 130 nm design rules. This is a significant advance beyond the 0.25 µm used in the e-DRAM of the Graphics Synthesizer in the PS2 while the logic rules have followed a standard path from 180 nm down to 130 nm.

This puts pressure on Toshiba as well as the e-DRAM tench cells were co-developed with them: ASC9 e-DRAM process that was then used for the Sony+Toshiba CMOS4 manufacturing process.


Dio, THAT pad limited ?

 

[Deadmeat]

...

Since the GIF bus is gone, SCEI saved over 100 pin outs. I am sure SCEI can take PSX2OAC even further.

 

[kaching]

If they're not accurate and just lie, Sony can sue them for damages. I don't think they're that naive, unless they can backup their claimed.

In a similar fashion, Sony has indicated EE+GS@90nm on their marketing material for the PSX, so if THEY are lying, they have customers that can sue as well.

So somebody is being naive here. Or just "creative" with their claims.

 

[Panajev2001a]

Good point... I seriously do not know how they could fit both EE and GS with 130 nm technology: the EE was 73 mm^2 in 150 nm technology and the GS in its 6th revision was 73 mm^2 in 130 nm technology.

Is it possible that the earlier designs were pad limited?

Dio, fitting those two chips in 90 mm^2 and 86 mm^2 with 130 nm and 90 nm manufacturing processes respectively... it makes me go uhm... really...

It is possible that the previous 2 designs were pad limited: this would explain why embedding them together at 130 nm they would be able to only go to 90 mm^2.

It is also possible that the design is once again pad limited and they cannot chave more than 4 mm^2 with the jump to 90 nm technology.

 

[V3]

This puts pressure on Toshiba as well as the e-DRAM tench cells were co-developed with them: ASC9 e-DRAM process that was then used for the Sony+Toshiba CMOS4 manufacturing process.

Yes it does.

 

[V3]

In a similar fashion, Sony has indicated EE+GS@90nm on their marketing material for the PSX, so if THEY are lying, they have customers that can sue as well.

Yes, like I said in my earlier reply the ramification is quite serious for Sony if this is true.

So somebody is being naive here. Or just "creative" with their claims

This claim doesn't give you room for creativity.

 

[Dio]

Is it possible that the earlier designs were pad limited?

Yes, its possible, since they pretty much stop at 73 mm2. So below that point they're probably pad limited, that's probably why even at 90nm process they still hover at 86 mm2.

So this makes perfect sense. 130nm is 90mm2 because previous designs were pad limited, 90nm only gets a little smaller because of the pad limit, but 90nm will have lower power/cooling requirements, seriously important for a console, when it tips up.

 

[Panajev2001a]

This puts pressure on Toshiba as well as the e-DRAM tench cells were co-developed with them: ASC9 e-DRAM process that was then used for the Sony+Toshiba CMOS4 manufacturing process.

Yes it does.

Maybe the story is like Dio said and they were pad limited in their 130 nm single EE and GS chips and combining together they could push the 130 nm manufacturing process to the point of only needing 90 mm^2 ( their manufacturing process could push more transistors per mm^2 than what they were using it for ).

The design might be once again pad limited and their 90 nm chips only shaved 4 mm^2... I did not think about it

Maybe they had worked the trench capacitor e-DRAM in 130 nm technology and they had to use 130 nm EE+GS chips as the yeld of their 90 nm process were not too great: likely we could probably examine PSX sold today and find real 90 nm chips in there.

 

[Panajev2001a]

Is it possible that the earlier designs were pad limited?

Yes, its possible, since they pretty much stop at 73 mm2. So below that point they're probably pad limited, that's probably why even at 90nm process they still hover at 86 mm2.

So this makes perfect sense. 130nm is 90mm2 because previous designs were pad limited, 90nm only gets a little smaller because of the pad limit, but 90nm will have lower power/cooling requirements, seriously important for a console, when it tips up.

You are right my friend, this and the idea of reducing density in the EE+GS@90 nm chip do make sense.

 

[V3]

Maybe they had worked the trench capacitor e-DRAM in 130 nm technology and they had to use 130 nm EE+GS chips as the yeld of their 90 nm process were not too great: likely we could probably examine PSX sold today and find real 90 nm chips in there.

They probably already did 130nm EE+GS and got 90mm2 @130nm, in order to promote their 90nm process they hide the fact that they did EE+GS@130nm at 90mm2 and just promote EE+GS@90nm at 86mm2.

It just sound more impressive to investor if you didn't know that the 90mm2 EE+GS@130nm existed

 

[Dio]

You are right my friend and I bow down to you

Well, it's all wild speculation. I can think of other possibilities - e.g. the 90nm core could be a little less dense than 130nm to reduce power density - but if the previous chips were known to be pad limited (and presumably many of those pads were used to communicate between the two chips) then the pad theory seems reasonable for now.

As for bowing down: I didn't realise what 'Dio' meant in Italian until after I'd started using the name, so you can cut that out

 

[Deadmeat]

...

Intel 845E

593 pinouts. Die size = small, very small.

I don't think PSX2OAC is pad count restricted, yet.

 

[Panajev2001a]

You are right my friend and I bow down to you

Well, it's all wild speculation. I can think of other possibilities - e.g. the 90nm core could be a little less dense than 130nm to reduce power density - but if the previous chips were known to be pad limited (and presumably many of those pads were used to communicate between the two chips) then the pad theory seems reasonable for now.

As for bowing down: I didn't realise what 'Dio' meant in Italian until after I'd started using the name, so you can cut that out

That is another interesting theory: we all say that Intel is very good at making dense chips, but looking at the power dissipation of Desktop CPUs I understand where they cut the corners ( for a modern chip PSUs of the order of 500+ Watts are not uncommon: Say Athlon 64 3000+ and Radeon 9800, add something else and you need all the juice a Vantec 520 Watts PSU can give ya ).

Ok, ok I will cut that out... man, people are so picky these days

 

[Panajev2001a]

V3, I was under the impression that until to the 130 nm node they were using stacked capacitor e-DRAM which they co-developed with Fujitsu and that the move ( as it is also presented in the ASC9 papers ) to trench capacitor e-DRAM happened with the jump to 90 nm technology.

Your theory of an EE+GS@130 nm might hold some truth: it might be something they green-lighted again once they saw that their 90 nm lines needed some more time ( delays with Nagasaki #2 ).

 

[kaching]

This claim doesn't give you room for creativity.

Nevertheless, someone has been creative here, because you have an accusation of a crime essentially. Sony either committed the crime or SI's accusation is false. Someone's reputation is on the line and, considering the cavalier way SI is handling it, I'm not so sure the whole thing is very clear cut.

 

[marconelly!]

Can someone tell me what does 'PSX2OAC' abbreviation means (I assume it's actually PS2OAC but Deadmeat had to 'translate' it)

 

[Panajev2001a]

Can someone tell me what does 'PSX2OAC' abbreviation means (I assume it's actually PS2OAC but Deadmeat had to 'translate' it)

In Deadmeat's own world that means PSX2 or PS2 On A Chip, which the EE+GS@90 nm is not ( there is more to PS2 other than the CPU and the GPU ).

The official name is EE+GS@90 nm whether Deadmeat likes it or not.