Deadmeat said:
EE block = 130 nm
GS eDRAM = 130 nm
GS logic block = 90 nm???(What do you gain by redesigning the GS logic block to smaller geometry when it didn't take up too much space in the first place?)
To help Sony's fabs gain experience-points with 90nm process-tech? Process-migration (of a part) is certain easier when the part's functionality is known and proven in an older process. Intel's first 0.13u CPUs to become available were the mobile Pentium3 and desktop/server Pentium3 (Tualatin.)
Can you mix and match different geometry on same die???
Yes. Nothing prevents a designer from putting larger-than-minimum transistor-structures on a die. Naturally, you'd expect someone to exercise a given process-node (90nm in this case) to its fullest. My guess is that Sony's e-DRAM process wasn't ready in time for their production deadline, so they switched to a more conservative 130nm e-DRAM cell-size (while continuing to refine 90nm in their development fabs.)
More generally, some companies have mixed process-nodes on a single wafer. Xilinx fabbed its Spartan2 using 0.25u for the transistor-logic, and 0.22u for the metal interconnect (and I think Trident Microsystems did the same for its Blade3D VGA.)
Well, this PSX2OAC(EE+GS@90nm) is mostly a 130 nm device based on Sony's own wording. I still don't understand why SCEI deviates from industry accepted standard and calls it a 90 nm device.
Strictly speaking, Sony didn't deviate from ITRS guidelines, as the guidelines refer to production-process and not the product itself. If any portion of the product contains 90nm transistor features, that's enough to validate the 90nm fabrication-line. 130nm equipment certainlly could not produce the chips in question, at any commercially usable yield-rate.
The fact that Sony's product (EE+GS@90nm), contains an unusually large portion lower-density logic, calls into question Sony's 90nm production-readiness.
This reminds me of Intel's "Coppermine" (0.18u Pentium3.) Intel introduced copper-interconnect (metal) at the 0.18u node. Most of the Coppermine's metal-layers used conventional (aluminum.) Only the top (highest) metal-layers used copper. Copper offers lower resistance and hence better performance than aluminum, but suffered from early production problems (due to its brittleness.)
“Nobody's been able to produce a 90-nm chip yet. I'm sure somebody will do it in 2004,†said Keyes.
Keyes' statement is rather sloppy for an 'industry expert.' It really should read "Nobody's been able to ship production-quality 90nm
logic chips yet." Xilinx has been shipping engineering-samples of its 90nm Spartan3 FPGAs for 3 quarters (9 months) now. And obviously, Intel has been struggling with the Prescott's
retail release. (Early engineering samples have been floating around for at least 6 months now.)
I wanted to say normally when you said say 90nm process, your gate length are also inlined with the guidelines. Well if not, your chip won't be very high in performance.
