PSX not at 90nm?
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asicnewbie
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Interesting, where did you find a die-photograph of the 845E? According to Intel's product-page, http://www.intel.com/design/chipsets/845e/index.htm?iid=ipp_browse+chpsts_845e&, the 845E is packaged in a flip-chip BGA.
In term's of I/O cell-count, flip-chip offers a potentially significant advantage over traditional wire-bond packaging. In wire-bond packaging, the I/O-cells must be placed in a 'ring' along the die's outer perimeter, facing outward. The most common placement is a simple (1 I/O-cell thick) ring. Most packaging handlers (and probably Sony included) can handle staggered I/O placement (where the ring thickness is 2 I/Os thick), effectively doubling the ratio of 'max-I/O-count' to 'minimum core-area.' (A die whose logic occupies less than the core-area is considered 'pad-limited', because the I/O-ring prevents further die-shrinkage.)
With flip-chip packaging, the I/O bond-sites can be (optionally) distributed across the die-surface, in a grid. Unlike the ring-I/O placement, grid-I/O placement doesn't force an lower-limit on the 'core-area size.' In short, if a flip-chip BGA uses grid-I/O placement, it won't be 'core-limited.'
A close-up die photograph (of the 845E and EE+GS@120nm) would clearly show the I/O placement strategy: ring or grid. In a ring-I/O die, thick power/ground stripes isolate the ring from the die 'core.'
Anyway, the jist of my post is, direct comparisons of flip-chip ICs is yet another exercise in futility.
Deadmeat said:
Interesting, where did you find a die-photograph of the 845E? According to Intel's product-page, http://www.intel.com/design/chipsets/845e/index.htm?iid=ipp_browse+chpsts_845e&, the 845E is packaged in a flip-chip BGA.
In term's of I/O cell-count, flip-chip offers a potentially significant advantage over traditional wire-bond packaging. In wire-bond packaging, the I/O-cells must be placed in a 'ring' along the die's outer perimeter, facing outward. The most common placement is a simple (1 I/O-cell thick) ring. Most packaging handlers (and probably Sony included) can handle staggered I/O placement (where the ring thickness is 2 I/Os thick), effectively doubling the ratio of 'max-I/O-count' to 'minimum core-area.' (A die whose logic occupies less than the core-area is considered 'pad-limited', because the I/O-ring prevents further die-shrinkage.)
With flip-chip packaging, the I/O bond-sites can be (optionally) distributed across the die-surface, in a grid. Unlike the ring-I/O placement, grid-I/O placement doesn't force an lower-limit on the 'core-area size.' In short, if a flip-chip BGA uses grid-I/O placement, it won't be 'core-limited.'
A close-up die photograph (of the 845E and EE+GS@120nm) would clearly show the I/O placement strategy: ring or grid. In a ring-I/O die, thick power/ground stripes isolate the ring from the die 'core.'
Anyway, the jist of my post is, direct comparisons of flip-chip ICs is yet another exercise in futility.
Panajev2001a
Veteran
Re: ...
Thank you for the good post
asicnewbie said:Deadmeat said:
Interesting, where did you find a die-photograph of the 845E? According to Intel's product-page, http://www.intel.com/design/chipsets/845e/index.htm?iid=ipp_browse+chpsts_845e&, the 845E is packaged in a flip-chip BGA.
In term's of I/O cell-count, flip-chip offers a potentially significant advantage over traditional wire-bond packaging. In wire-bond packaging, the I/O-cells must be placed in a 'ring' along the die's outer perimeter, facing outward. The most common placement is a simple (1 I/O-cell thick) ring. Most packaging handlers (and probably Sony included) can handle staggered I/O placement (where the ring thickness is 2 I/Os thick), effectively doubling the ratio of 'max-I/O-count' to 'minimum core-area.' (A die whose logic occupies less than the core-area is considered 'pad-limited', because the I/O-ring prevents further die-shrinkage.)
With flip-chip packaging, the I/O bond-sites can be (optionally) distributed across the die-surface, in a grid. Unlike the ring-I/O placement, grid-I/O placement doesn't force an lower-limit on the 'core-area size.' In short, if a flip-chip BGA uses grid-I/O placement, it won't be 'core-limited.'
A close-up die photograph (of the 845E and EE+GS@120nm) would clearly show the I/O placement strategy: ring or grid. In a ring-I/O die, thick power/ground stripes isolate the ring from the die 'core.'
Anyway, the jist of my post is, direct comparisons of flip-chip ICs is yet another exercise in futility.
Thank you for the good post
Yes, but now we sort of know that they can use trench capacitor eDRAM on 130 nm process too. Maybe they modified their 130nm process to cope with it.
I think it was green light for EE+GS@130nm all along. Its probably something they did before even trying EE+GS@90nm. It just they hide it, to make the result for 90nm node looks more impressive.
But still, if they claimed EE+GS@90nm for PSX, this is still a lied to consumers and investors, and Sony got some explaining to do.
nondescript
Regular
Re: ...
Beat me to it! You did a better job of describing it then I would have anyways. Comparing the two is apples and oranges.
asicnewbie said:Deadmeat said:
Interesting, where did you find a die-photograph of the 845E? According to Intel's product-page, http://www.intel.com/design/chipsets/845e/index.htm?iid=ipp_browse+chpsts_845e&, the 845E is packaged in a flip-chip BGA.
In term's of I/O cell-count, flip-chip offers a potentially significant advantage over traditional wire-bond packaging. In wire-bond packaging, the I/O-cells must be placed in a 'ring' along the die's outer perimeter, facing outward. The most common placement is a simple (1 I/O-cell thick) ring. Most packaging handlers (and probably Sony included) can handle staggered I/O placement (where the ring thickness is 2 I/Os thick), effectively doubling the ratio of 'max-I/O-count' to 'minimum core-area.' (A die whose logic occupies less than the core-area is considered 'pad-limited', because the I/O-ring prevents further die-shrinkage.)
With flip-chip packaging, the I/O bond-sites can be (optionally) distributed across the die-surface, in a grid. Unlike the ring-I/O placement, grid-I/O placement doesn't force an lower-limit on the 'core-area size.' In short, if a flip-chip BGA uses grid-I/O placement, it won't be 'core-limited.'
A close-up die photograph (of the 845E and EE+GS@120nm) would clearly show the I/O placement strategy: ring or grid. In a ring-I/O die, thick power/ground stripes isolate the ring from the die 'core.'
Anyway, the jist of my post is, direct comparisons of flip-chip ICs is yet another exercise in futility.
Beat me to it! You did a better job of describing it then I would have anyways. Comparing the two is apples and oranges.
notAFanB said:
Well, assuming the report is accurate and the chip(s) they have tested are 130nm chips the question is are they all 130nm or are there some 90nm versions in production as well and they are just mixed? Was the sampling just bad luck or does it reflect everything?
I find that hard to swallow.V3 said:
I could believe the original explanation - Inadvertent false advertising, eg. they couldn't get 90nm to work on time - and were caught with pants down when it happened, so they attempted to quietly skirt the issue rather then admitting the problem...
But what you suggest - to brag with PR of 90nm chip in PSX for 8months, while planning for that entire time NOT to use 90nm at all, that's pushing it (unless in Sony exec land, false advertising is legalized).
jvd said:
As usual you have completely missed the points made, opting for your usual "Sony fanboi VS everyone else" approach. Unsurprisingly.
No one is saying this story is not true.
The point here is that people are accusing Sony of lying since the beginning. They are saying that Sony has been lying about using 90nm and were planning to use 130nm all the way from the beginning, although advertising for 90nm.
Of that, there is no proof. And it is also very very unlikely that the same has happened.
If Sony got caught into something and could not complete the 90nm process, and opted for the moment to use a 130nm one, now that's more likely.
One corporation does not to lie for 8 months and plan to use a process while advertising another. All behind people's backs. KNOWING they would be found out.
Really, someone needs a reality check.
...
So SCEI lied to public. Does it negatively affect consumers who purchased "PSX"? No. But it does cast doubt on SCEI's ability to successfully migrate to advanced fab processes and meet its claims made in public.
The lesson of this fiasco is that SCEI is not very trustworthy, any claims made by SCEI representatives should be met with skepticism.
Doesn't Enron mean anything to you??? You have too much trust in big corporations, because SCEI is one of the least trustworthy of major corporations in terms of honesty about its figures and marketting. Remember "66 million polygons/s(TM)" and "Toy Story in Real Time(TM)"? It wasn't not so long ago that Kutaragi and Co were preachnig "Teraflop on a chip(TM)" and "1000x the power of PlayStation2(TM)".
PSX2OAC's official name is "EE+GS@90 nm". SCEI made a press release about how this was the world's first mass produced 90 nm part, only to find out that it wasn't a 90 nm part.
So SCEI lied to public. Does it negatively affect consumers who purchased "PSX"? No. But it does cast doubt on SCEI's ability to successfully migrate to advanced fab processes and meet its claims made in public.
The lesson of this fiasco is that SCEI is not very trustworthy, any claims made by SCEI representatives should be met with skepticism.
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