Hmmm. I was going by
this article which quotes the power consumption for the A8 at <0.59mW per mhz.
0.59 * 600 = 354mW
But maybe that figure wasn't a peak figure...or maybe it's just plain incorrect? I've no idea what typical mobile CPU power draw is like, I went looking for the 3GS's to get an idea, and that's the first set of numbers I came across...
edit - it doesn't seem crazily out of whack with the kind of numbers quoted in the other B3D article I linked to in my last post either, which says 'full-system power consumption of ~3W' for a symbian s60, for example (suggesting chipset consumption in these kinds of phones is sub-1W). Now it may be I'm totally misunderstanding how this stuff works..(?) :|
First of all... this might be helpful...
http://processors.wiki.ti.com/index..._Spreadsheet#Section_E:_FULL_CHIP_POWER_TALLY
It allows you to calculate power consumption numbers for the CortexA8 included in the OMAP3 line, NEON SIMD included, and other components of the OMAP3 SoC.
At 750 MHz and with 90 % utilization of the ARM core we get about 0.9W (~1W if you consider 100% utilization) using that XLS file... assuming I am using it correctly.
At 500 MHz the power consumption is almost half that so... it is possible that with some custom work you might be able to raise the clockspeed without raising voltage as much.... as it is happening in that chart (higher than linear scaling in power consumption).
Let's start from this again... I think that is the Schmoo plot for the 90 nm SPE's. Let's take 1W for the lowest combination of frequency and voltage available: 2 GHz and 0.9V.
(another thing to thin about is that big savings for a mobile CELL will come from the shift from XDR to a more power efficient but less performing alternative and the FlexIO connection to the rumored SGX core might receive a downgrade in bandwidth too... although I hope they fix the CPU <-- GPU bandwidth over the few MB/s mark... especially since PSP2 will likely be a UMA solution... still my point is this: between external I/O interfaces and memory I/O a mobile CELL could save a lot of power compared to PS3 CELL)
Going from 90 nm to 65 nm the over-all power consumption for the CELL chip went down by 19% and going from 65 nm to 45 nm power consumption went down by yet another 40%.
CELL is probably already going the 32 nm shrink route and testing the 32 nm manufacturing process with a small and higher yield mobile processor like what the PSP2 needs could help to make the case for mobile CELL in PSP2. So we could see another power consumption drop that we still need to consider... say 30%?
1W -> 0.81W -> 0.486W -> ~0.34W for the "made up" 32 nm version (are real numbers available?)... the original 1W per SPE was the 2 GHz power consumption at 90 nm, just to think about that value again.
I also doubt that the PSP2 processor will push for >1 GHz clocks... it might even be happy with 800 MHz or less (4 SPE's at 800 MHz pack a lot more punch than any other mobile CPU planned in the near future). Even if the iPhone 4G goes with the iPad's A4 at 1 GHz, a 4 SPE's powered PSP2 CPU might even be happy with 600 MHz for the CPU and still have a lot of performance headroom over the A4 to be able to stand more iPhone specifications upgrades (4G, 4GS, etc...).
So, 800 MHz... say that we cut that number in half from its 2 GHz power consumption? We are being conservative, looking at that schmoo plot again and the power consumption difference between 2 GHz and 4 GHz... which doubles with the doubling of frequency... except when we talk about rising voltage, in that case the power consumption at 4 GHz is 3x than at 2 GHz... so we could get even less than that by lowering the voltage.
So, maybe a 0.1W per SPE solution at 32 nm is possible.
Let's say that the main CPU core chosen takes another 0.1W... 0.5W for 4 SPE+main CPU core.
It does not seem so far fetched, but maybe I am missing some major details here and people with more insights on the matter can spot the many mistakes made.
A CELL based CPU would work very well alongside a PowerVR TBDR... most of the vertex work could be done by the SPE's (thanks to years of experience with EDGE libraries and other solutions, developers are accustomed to do vertex work there) and let the SGX do what it does best: HSR and pixel shading (mostly as I do not think the USSE2 pipes would be used for pixel shading only.)