PlayStation III Architecture

[V3]

someone please explain what the original article says (or the current understanding) of how many processing elements/cpu cores/FPUs/thread units etc, the PS3 is now thought to have. how many processors per Cell, etc - meaning the basic architecture. if possible. because it's very unclear to me, and probably many readers as well.

Well I posted it before here, of what the possibility of what PS3 might be, its from that patent.

[0072] Using this standardized, modular structure, numerous other variations of processors can be constructed easily and efficiently. For example, the processor shown in FIG. 6 comprises two chip packages, namely, chip package 602 comprising a BE and chip package 604 comprising four VSs. Input/output (I/O) 606 provides an interface between the BE of chip package 602 and network 104. Bus 608 provides communications between chip package 602 and chip package 604. Input output processor (IOP) 610 controls the flow of data into and out of I/O 606. I/O 606 may be fabricated as an application specific integrated circuit (ASIC). The output from the VSs is video signal 612.

There are several other example configuration in the Patent application.

Note also they name the new chip Broadband Engine.

I am a bit busy at the moment, maybe later, for breakdown, but that's a pretty straight forward, Patent are quite easy to read.

 

[Tagrineth]

Patent are quite easy to read.

 

[Kolgar]

Well, Mr. David South! I see you've migrated as well?

Kolgar

 

[Ty]

Of course it's easy to read. It's understanding them that is difficult.

 

[megadrive0088]

Well I posted it before here, of what the possibility of what PS3 might be, its from that patent.

Quote:
[0072] Using this standardized, modular structure, numerous other variations of processors can be constructed easily and efficiently. For example, the processor shown in FIG. 6 comprises two chip packages, namely, chip package 602 comprising a BE and chip package 604 comprising four VSs. Input/output (I/O) 606 provides an interface between the BE of chip package 602 and network 104. Bus 608 provides communications between chip package 602 and chip package 604. Input output processor (IOP) 610 controls the flow of data into and out of I/O 606. I/O 606 may be fabricated as an application specific integrated circuit (ASIC). The output from the VSs is video signal 612.


There are several other example configuration in the Patent application.

Note also they name the new chip Broadband Engine.

I am a bit busy at the moment, maybe later, for breakdown, but that's a pretty straight forward, Patent are quite easy to read.

Ok thanks for pointing that out.


yeah i do see how the term Broadband Engine might probably be the CPU/Cell(s) configuration for PS3 (what used to be referred to as Emotion Engine 3) and then the so called Visualizer or Visualizers are the graphics processing elements (maybe what used to be referred to as Graphics Synth 3)

of course, there are so many possibile configurations/combinations of possibilities for the final PS3, it would be impossible for me or for anyone to get into them all here.... ahhhh

well hey, at least something to chew on now


it seems from what i am understanding that what is currently thought to be a Cell (a PE right?) consists of 1 PPC core plus 8 Vextor Units plus memory, buses and other stuff to glue it together. 4 of these Cells/PEs will form a Broadband Engine (what could be called EE3) - each Cell/PE would produce about 256 GFLOPs @ 4 GHz thus a Broadband Engine would produce over 1 TFLOP.

I do kinda agree with people in this thread that it's possible that the final PS3 cell chip configuration could take one more leap, but not in MHz (that's already high enough) but in number of Cells/PEs to reach multi-Teraflop performance. perhaps each Broadband Engine (4 Cells) is the Cell Chip (1 die) that ive heard of, and the final PS3 will have several of these Broadband Engines/Cell Chips. but again, there are so many possibilities, and even that article says the final configuration for PS3 is up in the air.

ok, i suppose that is enough speculation for now

 

[Gubbi]

The PEs primary task is to send/receive program and data packets, and to control locking of chunks of the central (512Mbit) memory together with dispatch to the APUs. The real work is then done by the APUs.

That is how I read the patents anyway.

This architecture is likely to fit streaming data problems fairly well (such as network packet processing and rasterization). But as a general purpose processor there seems to be alot of overhead with only 128KB scratch pad memory, everything else has to be communicated in packets through a PE. Getting good single thread general purpose performance seems unlikely.

Cheers
Gubbi

 

[_phil_]

Tagrineth :

agreed .
But my point was that assets are in this generation 70-80 %
of production time.When i started to work on 3d games,i could make one 400 polygon character + skin in 2 days (2-3 a week),animated with autowelded local rotations.next gen ,a character ,on next gen hardware will have probably 30000 to 50000 polygon with multiples hires textures and combiners +30 -80 bones +more complex hair system (witch is particulary long to do).
Asset creation sure wil stretch heavily.

 

[Grall]

Phil:

Surely, not having to worry so much about how to best use your limited poly budget must reduce some of that workload? Besides, modelling and animation tools should have gotten considerably better too...

Not saying it compensates completely for the increased complexity of course, but it shouldn't ONLY be an increase, right?


*G*

 

[BenSkywalker]

Surely, not having to worry so much about how to best use your limited poly budget must reduce some of that workload?

I can select a menu option to reduce poly counts in the apps I have. May not be perfectly ideal reduction, but it only takes a few seconds. Artistic talent is going to be paramount next gen, likely far more important then which platform you are working on.

 

[_phil_]

grall:

sure,but overall ,it is certainly a BIG increase.Imagine , you have to add such things as cloth and hair physic-driven simulation or eventually lip-sync will be standard...

providing UVs for for a 50 000 poly character is an unfun joke

for scenes ,we could say that the whole polycount and texture count for a level wil be standard for one room.

this generation allready suffer by the heavy data needs:dev time increases , playtime shrinks and costs goes way Up.

this is why i don't vote for big memory size ,i'd rather advocate for intelligent interpretation of shading networks builded on procedural generators directly out of maya ,for exemple. this could provide solution for 90% of hand made bitmaps(photoshop) .

Same thing for modeling:subivision surfaces are the way to go since you can control LOD dynamicaly.It still takes much more time to build up.

 

[megadrive0088]

I was hoping to find some of the posts which speculated that PS3's varient of CELL would consist of dozens of smaller Cells and hundreds or thousands of sub-processors I guess that was a bit too far fetched, now, with the likely reality of a PPC core (or a few PPC cores) and 32 APUs/VUs. still, that's a large step beyond PS2, especially if they manage to reach 4GHz.

 

[tuna]

This is not really related to the patents, but anyway....

In the latest Nikkey Weekly, it said Toshiba asked Sony for 200 billion yen for the chip-factory for the PS3. And it said it would be operational 2004.

So, do you think that the PS3 will be released in Japan spring 2005 and in the rest of the world in the autum. It seems like everything is pointing towards that......

 

[V3]

Of course it's easy to read. It's understanding them that is difficult.

OK. However, they are easier to understand than say some tech document.

it seems from what i am understanding that what is currently thought to be a Cell (a PE right?) consists of 1 PPC core plus 8 Vextor Units plus memory, buses and other stuff to glue it together. 4 of these Cells/PEs will form a Broadband Engine (what could be called EE3) - each Cell/PE would produce about 256 GFLOPs @ 4 GHz thus a Broadband Engine would produce over 1 TFLOP.

The patent doesn't suggest anything about the PPC core and 4 GHz clockspeed. APUs aren't exactly Vector Units either.

Also this time around it seems the Visualizer contained APUs for programmable T&L it seems. The Pixel engine mentioned in the Visualizer, could be something like GS on PS2, but I think it need to be soup up to keep up with the BE.

But in that statement they did say they put 4 Visualizer on one chip so I don't know.

Also for the DRAM, it seems going to be 64 MB per chip. Those APUs are capable of accessing DRAM from their adjacent chip. As far as I see it, they don't seem to require external RAM, like RAMBUS.

The patent also talk about how they deal with backward compatability. So they are predicting faster hardware yet.

The PEs primary task is to send/receive program and data packets, and to control locking of chunks of the central (512Mbit) memory together with dispatch to the APUs. The real work is then done by the APUs.

Its the PUs. The PEs is the PUs, DMAC and that 8 APUs.

Also the guy who filed the patent, Suzuoki Masakazu, he is the guy that work on Playstation, and probably one of the head guy for Emotion Engine and PS2, so not suprised if this so called invention have something to do with PS3.

Anyway none of this is final, but the architecture is not going to deviate too much.

Well if PS2 is complex, this with 50+ processors are going to be tough

 

[zurich]

Nice summary from arstechnica.com:

Posted 1/10/2003 - 12:23AM, by Hannibal
A few people pointed this out to me in email, and then I spotted it over at the Inquirer today, too. It seems that a patent filed by Sony on September 26, 2002, lays out in pretty good detail the architecture of the upcoming Playstation 3. Now, I've not had a chance to pore over this patent in the way that I'd like, but I have spent some time with it and I can say that there's a lot of fairly specific information there that fits well with what has been reported on the PS3, so far. In fact, there may be enough there for a decent article on the technology and philosophy behind the PS3, if not the actual device itself. But I wouldn't even consider such a thing until I'm done with my current project, which is part II of the PPC 970 article.

In brief, it looks like the PS3 will be made up of four "processing elements," or PEs, each of which will contain a DMA controller, some local cache and about eight vector units. These PEs will be fully connected to 64, 1MB banks of DRAM, and will be under the control of a (probably PowerPC) CPU that dynamically allocates code to run on the various PEs according to workload. The code that runs on the PEs comes in the form of "software cells," which are small programs with unique IDs. These cells can actually be run on any PE (since the PEs are uniform in ISA) located anywhere on the network, so if the master CPU can't find enough free resources to run the cell on the local machine it can send it off (along with the data that it needs) to another machine for servicing.

Anyway, I could talk a lot more about this thing based on the patent info alone, but I'll save that for a future article. In the meantime, if anyone has any kind of PS3 info they'd like to send my way, please do so. I'd love to do another in-depth series on the device like I did with the PS2. In fact, I half think Sony should show me some serious love for those articles, because their English-language docs for the PS2 were so notoriously bad that I've heard from numerous game developers that my articles served as the kind of de facto standard introduction to the console until fairly recently, when decent literature finally became available.

Hannibal's a really, really smart guy. I hope he writes up a full-blown article in the future.

edit: EIGHT vector units per PE?!?

 

[Guest]

IS SONY GIVING AWAY TOO MUCH INFORMATION Too early? MS will now have more than enough knowledge to kick their asses again?

We certainly have no idea how Xbox2 will work so far.

 

[marconelly!]

We certainly have no idea how Xbox2 will work so far.

Yeah, like THAT is so hard to imagine...
It's either Intel or AMD plus either Nvidia or ATI. You can even predict what CPU/GPU it would have by their well know development cycles.

MS will now have more than enough knowledge to kick their asses again?

Again? I don't recall any show-off between MS and Sony where they kicked their ass.

 

[Guest]

Yeah, like THAT is so hard to imagine...
It's either Intel or AMD plus either Nvidia or ATI. You can even predict what CPU/GPU it would have by their well know development cycles.

Maybe, maybe not. There are rumors that MS wants to do the hardware themselves, that like PS3 will work with full software rasterization.
So what CPU/GPU Xbox2 will have?

Again? I don't recall any show-off between MS and Sony where they kicked their ass.

PS2 certainly had their asses kicked by Xbox1.

Good luck to developers coding for PS3. DX10/11 suddenly sounds so sweet.

A good PS3 discussion going on here
http://arstechnica.infopop.net/OpenTopic/page?q=Y&a=tpc&s=50009562&f=174096756&m=1280946545&p=1

 

[marconelly!]

PS2 certainly had their asses kicked by Xbox1.

Wow! And Xbox will have it's ass kicked by some other hardware released one year after. Wait, that already happened with Radeon 9700 and GeForce FX.

I'm sure Microsoft would gladly switch sides here, to have the older hardware that sold more, instead of having a geek bragging rights with a one year newer machine. Selling ten times less units is something I would hardly call an ass kicking...

 

[megadrive0088]

It's either Intel or AMD plus either Nvidia or ATI. You can even predict what CPU/GPU it would have by their well know development cycles

Ya, well said! haha. how true.

as for the other possibility (MS making their own GPU/CPU) that's the only wild card.

 

[Guest]

But we are speaking of hardware here marc, hardware, not sales.
Sony showing so much of their cards so early can only be good for MS.