PlayStation III Architecture

[MfA]

One cell could be allocated to doing transforms on graphics in that memory and it gets the lion share of the memory? While another cell which is allocated to AI functionality doesn't bother allocating much of that memory for its workload?

isn't this difficulty what GRID based computing is?

That is no more accurate than to say it is the same difficulty you have with superscalar execution. With GRID computing the problems are partitioned much more coarsely, this has more to do with say something like Charm++ than GRID.

 

[Vince]

Cool, so whatcha think Marco?

 

[MfA]

I still dont quite see why my toaster would need to share the PS3's computing power through a fiber optic link. The Cell concept as far as the network architecture goes is not very usefull to consumers beyond simply making the PS3 a central server for thin clients to use around the house, but Id rather stick with an open architecture for my home computing needs ... but weve been over that before The patent is not too exciting, connecting parallel processors by fiber is old hat. Apulets sound innovative until you realise they are objects. I think most of the patent is just a land grab.

The insider comments are the most interesting thing, but they are the least reliable. Still 256 GFLOPs per chip sounds at least reasonable (my oft expressed guess has been 200 GFLOPs for almost 2 years now).

 

[V3]

The insider comments are the most interesting thing, but they are the least reliable. Still 256 GFLOPs per chip sounds at least reasonable (my oft expressed guess has been 200 GFLOPs for almost 2 years now).

I think the insider comments are made from the fact it stated in patent that each APUs is preferably capable of 32 GFLOPS. Since each PE should preferably have 8 APUs, that's how they get 256 GFLOPS.

Also 4 GHz from the fact that each APUs have 4 floating point units. If these floating point units are Multiply add, 4 GHz would give 32 GFLOPS.

Compare this to the old cell which have 1 Multiply Add @ 500 MHz, its a step up in claim.

Regarding memory, each of those APUs have its own memory as well besides the central memory. And those local memory aren't cache either.

I still dont quite see why my toaster would need to share the PS3's computing power through a fiber optic link.

LOL, what make you think you need a toaster, PS3 will probably double as your toaster

 

[Gubbi]

I still dont quite see why my toaster would need to share the PS3's computing power through a fiber optic link.

LOL, what make you think you need a toaster, PS3 will probably double as your toaster

Amen.

With 4 PEs each with 8APUs, each capable of a 4 way SIMD FMADD @ 4GHz. .. First mass market kilowatt chip ?

Or maybe it'll be @ 1GHz.

Cheers
Gubbi

 

[mech]

If it is 4Ghz - ner ner, toldya so

 

[zidane1strife]

I still think that's certainly not final... a gut feeling tells me the final processor will be one order of magnitude higher....

 

[Gubbi]

And my gut feeling is that you are insane.

Stuffing 128 FMADD units on one chip together with 512Mbit of memory (and the stuff to connect it all) AND make it all run @ 4GHz without vapour phase cooling is ambitious even for 2005.

Cheers
Gubbi

 

[randycat99]

An order of magnitude greater than 4 GHz??? Bite your tongue!

I'm amazed even by 4 GHz (but I have no concept of what 2-3 years from now will be like). I still think 1 GHz is still more believable, but I guess when you got it, might as well flaunt it...

 

[V3]

[0072] Using this standardized, modular structure, numerous other variations of processors can be constructed easily and efficiently. For example, the processor shown in FIG. 6 comprises two chip packages, namely, chip package 602 comprising a BE and chip package 604 comprising four VSs. Input/output (I/O) 606 provides an interface between the BE of chip package 602 and network 104. Bus 608 provides communications between chip package 602 and chip package 604. Input output processor (IOP) 610 controls the flow of data into and out of I/O 606. I/O 606 may be fabricated as an application specific integrated circuit (ASIC). The output from the VSs is video signal 612.

That could be the configuration of PS3.

Broadband Engine and Visualizer probably the buzzwords.

Stuffing 128 FMADD units on one chip together with 512Mbit of memory (and the stuff to connect it all) AND make it all run @ 4GHz without vapour phase cooling is ambitious even for 2005.

Not only that, but they want each of that APUs to have its own 128kB of memory. Plus all those wide buses. I don't think it will be 2005. Maybe end of 2006 or 2007.

But they also said, it is possible to split it into two chips, since it has modular design.

I still think that's certainly not final... a gut feeling tells me the final processor will be one order of magnitude higher....

Yeah probably not. But that example that they give, seems to be faster than GScube already.

 

[Vince]

I don't think it will be 2005. Maybe end of 2006 or 2007

I think late 2005 is basically it though. What size tranistor budget will you need? I was just reading how some are already designing a 100M gate device using a 90-nanometer process. Assuming a 65-nm SOI process, as a previous Toshiba release on eDRAM stated, what are the tranistor and thermal limits? How far is 45-nm away?

Does anyone have a chart or similar of the net increase in density, speed, and power consumtion reduction with each new process? I forget this stuff to fast...

Actually, come to think of it. Wasn't Intel saying they will achieve 10Ghz and something like 400M tranistors by 2005 a year or two ago?

 

[V3]

I think late 2005 is basically it though. What size tranistor budget will you need? I was just reading how some are already designing a 100M gate device using a 90-nanometer process. Assuming a 65-nm SOI process, as a previous Toshiba release on eDRAM stated, what are the tranistor and thermal limits? How far is 45-nm away?

Well you don't really go by transistor count, but chip size.

Just for that eDRAM 64 MB of eDRAM you need about 500 million. DRAM is actually cool and dense. So it will actually take little space, than the number suggest.

Then they want some for local memory which is 128kB for each APUs, which is about 4 MB. This going to be SRAM. Which is about 250 million transistors. Using 0.10 process this would take more than 1 cm2.

Now those buses, which is pretty damn wide and all the logic would need to be around 300 million transistor, if the chip is to be around 4 cm2.

They can do it in 2005, but they can get into supply problem like they did with PS2, this time around MS is on their tail, supply problem is really bad from business point of view.

Actually, come to think of it. Wasn't Intel saying they will achieve 10Ghz and something like 400M tranistors by 2005 a year or two ago?

I thought it was 2010.

 

[zidane1strife]

An order of magnitude greater than 4 GHz??? Bite your tongue!

No I mean Tflop performance... In other words I think the final desing will be capable of 10Tflops.

 

[Johnny Awesome]

 

[megadrive0088]

someone please explain what the original article says (or the current understanding) of how many processing elements/cpu cores/FPUs/thread units etc, the PS3 is now thought to have. how many processors per Cell, etc - meaning the basic architecture. if possible. because it's very unclear to me, and probably many readers as well.

much appreciated!


Edit: as for memory, here's what i think. the 64MB is just for the 4 Cells alone. it's eDRAM. can be thought of as L2 cache. there should be another amount of eDRAM for the Graphics Synthesizer3 (now being called Visualizer) as well as a large amount of main system memory that can be used by both the Cell(s) and the graphics processor(s) ...say anything from 256MB to 1 GB of Rambus Yellowstone RDRAM.

 

[Guest]

Will it do jaggies shading again?
PS3 should be able to support 720p and 1080i well this time.
Look for at least 512mb of ram + 64mb of embbed ram if PS3 wants to be a multimedia setop box and to give Xbox2 some competition.

 

[megadrive0088]

you mean 512 MB main mem and 64 MB eDRAM

(MegaByte not megabit)

right?

 

[_phil_]

Will it do jaggies shading again?
PS3 should be able to support 720p and 1080i well this time.
Look for at least 512mb of ram + 64mb of embbed ram if PS3 wants to be a multimedia setop box and to give Xbox2 some competition.

how many developpers will be able to fill that much ram in realistic production time-frame ?

making datas for nextgen will be very problematic...
i predict much shorter games ...

 

[Tagrineth]

Will it do jaggies shading again?
PS3 should be able to support 720p and 1080i well this time.
Look for at least 512mb of ram + 64mb of embbed ram if PS3 wants to be a multimedia setop box and to give Xbox2 some competition.

how many developpers will be able to fill that much ram in realistic production time-frame ?

making datas for nextgen will be very problematic...
i predict much shorter games ...

The point isn't so much to fill it but to have enough space that your vision shall never be stifled.

Imagine how much more enormous some games like Metroid Prime could have been with four times the RAM...

Also the more RAM you have, the less compression you NEED, which of course results in faster in-game load times and memory accesses. Of course disc optimisation of some kind will be necessary but that's probably what the HDD will be used for, a load buffer, like Xbox.

 

[David_South#1]

Greetings AlexOK, and people of this forum.

Greetings AlexOK, and people of this forum.

I have to go out now there is this thing with Grilled burgers and Rocky the movie happening. But will return later to add what I have to contribute. First I want to point out that 64MByte eDRAM is a little unreasonable. I was originally expecting 8MB to 32MB of eDRAM. 64Mbit=8MB is more realistic.

In the mean time you can visit.
http://forum.pcvsconsole.com/viewthread.php?tid=12&page=44 Roam around and have some fun, I'll see you again soon. Thanks from DS#1.

BTW-I'm David_South but was unable to log in as him?
Something about having the wrong email address? ;P