Phenom video leaks from Lake Tahoe

The 40% was AMD's PR being very selective about estimated performance on tests they never fully disclosed.
There are a few areas where Barcelona's performance scales well enough that it can boast a higher amount of performance at a given clock speed.

The catch is that it is in a multisocket system on bandwidth-limited FP benchmarks.
There, Barcelona fared better versus the Core2 systems at the time of their estimates a half year ago.

Sadly for Phenom, those advantages don't really apply in the single-socket desktop market, and seem to work against it.
 
The 40% was AMD's PR being very selective about estimated performance on tests they never fully disclosed.
Well, they did say "in various workloads". I guess their definition of "various" is just a "bit" different than ours :)
Sadly for Phenom, those advantages don't really apply in the single-socket desktop market, and seem to work against it.
I wouldn't say they work against it, just that desktop doesn't depend on memory bandwidth and x87 performance all that much.
 
I wouldn't say they work against it, just that desktop doesn't depend on memory bandwidth and x87 performance all that much.

There is little benefit for the current 3-level cache setup when you don't have to worry about coherency traffic.
The L3 cache, for current steppings, has essentially erased the latency benefit of the IMC.

The A64 has enjoyed a ~20 ns latency advantage over Core2.
The L3 for Phenom right now has an additive latency of ~20 ns.
 
It makes one wonder that with AMD's relatively limited available R&D resources (compared to Intel) if they focused almost solely on the server and multi-processor market while hoping that any breakthroughs in that area would filter down to the desktop market.

As it certainly appears to be the case at first glance. All these changes should keep AMD ahead in the 4+ processor server market, however it doesn't appear to be doing much for the single processor desktop market.

Regards,
SB
 
How feasible would it be for them to remove the L3 and unify the L2? I suppose that would be a major re-working of the layout. :???:
 
How feasible would it be for them to remove the L3 and unify the L2? I suppose that would be a major re-working of the layout. :???:

I wish they would release such a part, but doubt we'll ever see a unified L2 part from AMD (not this generation anyway). Ditching the L3 probably will happen for low-end parts though. Obviously the L3 is detrimental to performance outside of server/HPC workloads so the scenario you described would likely bring Phenom back to near-parity with Intel's Quads, IPC-wise anyway.
 
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