Official PS3 Thread

[Saem]

I agree.

Emphasis will be on using die area for execution units and to keep these units fed. I'm guessing an APU will be a simple inline dual issue core which can issue one op to the SIMD array and one load/store op per cycle.

I disagree.

I think with the die size the way it is and the rather aggresive clock rates, I think the hardest thing might be syncronization. With the feature size involved it seems that wire delay is going to be a bigger problem.

I think replicating units will be easier than clocking high -- to a degree of course.

I'm thinking the 1GHz <= clockrate <= 2GHz is what you're looking at -- I'm leaning for lower on that scale.

 

[MfA]

The main problem with high clocks isnt so much wire delay IMO. the individual cores are trivial compared to desktop processors, getting signals across them isnt a big issue, and for inter core communication wire delay doesnt pose much of a problem.

Power consumption is a bigger problem.

 

[Saem]

The cores can be internally syncronised fairly easily, I agree there.

I'm having trouble seeing how it'll be easy to make a small net which will be used to syncronize each core.

 

[V3]

I'm thinking the 1GHz <= clockrate <= 2GHz is what you're looking at -- I'm leaning for lower on that scale.

We don't know the clockrate. But we know they are aiming for 32 GFLOPS per APU. It could be 500 MHz for all we know.

Power consumption is a bigger problem.

Half the chip is eDRAM, so heat dissipation shouldn't be too big of a problem.

I'm having trouble seeing how it'll be easy to make a small net which will be used to syncronize each core.

Each APU doesn't really need that strict synchronisation.

 

[Gunhead]

To get 32 GFLOPS per APU, hmm, if we assume 1 GHz clock speed, and count FMAC as 2 ops, we need 16 FMAC units per APU.

That would be four SIMD units (each like PS2's VU) per APU. (As opposed to just one SIMD unit = four FMACs per APU.)

Like I said in my little "analysis" up there a page ago 8)

But the point here is that they hardly can put more than 16 FMACs into one APU, so unless they are counting other floating point hardware (FDIVs and the sort) not in those diagrams, they'll need 1 GHz for the 32 GFLOPS figure! Don't they?

In other words, doesn't the (assumed) 32 GFLOPS figure give us the minimum clock speed -- 1 GHz?

 

[V3]

That would be four SIMD units (each like PS2's VU) per APU. (As opposed to just one SIMD unit = four FMACs per APU.)

It doesn't have to be four SIMD units. They can put 16 FMAC in a single SIMD units. They can put extra APUs or they can put extra PEs. The best scenario is to go for clock speed, than you get a good TFLOPS 8)

 

[Gunhead]

Okay, okay

It would be interesting if the APUs could juggle 512-bit vectors as easily as 128-bit vectors. Some bignum math researches might be interested in porting Linux to it...

Personally I'd prefer added parallelism to ridiculous clock speeds, although where I live it sometimes gets cold in the winter

 

[Paul]

Interesting "news" from Spong.

http://spong.com/index.asp?art=5014

Sony executive deputy president Ken Kutaragi has made some revealing pledges relating to the firm’s planned investment into the CELL processor, the mysterious chip that will power the PlayStation 3, when it launches in several years time.

Kutaragi said that Sony is poised to invest a staggering 500 billion yen into processor development in the coming years, and even more impressively, he pledged 200 billion yen to the CELL project, a figure equating to $1.7 billion. If anything, this illustrates just how crucial the PlayStation 3 project is to the future of the entire Sony empire.

"The Sony group as a whole procures about 1 trillion yen worth of semiconductors annually, and the amount will probably keep increasing in the coming yearsâ€￾, Kutaragi stated.

This news has again rattled analysts, as it seemingly pushes back the projected release date of Sony’s next home console. There is also concern for Sony’s massive market share it now enjoys as the price of the PS3 looks set to skyrocket in comparison with Microsoft’s offering.

Indeed, the Xbox 2 will almost certainly have an off the shelf high-end Pentium processor, that will simply involve buying units from Intel, and applying them to the new machine, a massive saving that can, and will, be passed down to consumers.

Kutaragi also said that if the PlayStation 2, and the new model of the machine in its irresistible new PSX guise, goes above its projected revenue in the next eighteen months, more than 200 billion yen would be pumped into CELL. However, what Sony must understand is that this money, an absolutely unparalleled amount to plough into the R&D for a games machine chip, must eventually be recouped from the consumer. If PS3 costs so much more to develop than Xbox 2, doesn’t the firm run the risk of leaving itself no option but to price itself out of the market?

We’ll bring you everything on all next-gen movers and shakers, right here, as it breaks.

I may be mistaken.. But isn't sony putting 200 billion yen into Cell old news that happened a month ago?

What does Spong think they are acomplishing by posting a month old news? Or did they just discover this now..

And how does putting money into a chip push back it's release date? And did Spong even look at the fact that Cell is currently slated to go into mass production early 2004?

I think this is more garbage from the same website who said that the PS3 specs would be released GDC 2003..

 

[V3]

Personally I'd prefer added parallelism to ridiculous clock speeds, although where I live it sometimes gets cold in the winter

Rightly so, you would have to stay out in the cold, with parallelism invading your living space. 8)

 

[Saem]

Each APU doesn't really need that strict synchronisation.

Are you sure? How strong is the coupling. Especially, in terms of accessing memory et al. If the cores are meant to communicate a lot -- which I'm pretty sure they will be -- they'll need good syncronisation unless they're using async communication like a lot of high performance MPUs these days.

 

[megadrive0088]

Spong is just misconstruing things, probably. Or just being pessimistic, injecting their own speculations to confuse matters to make them seem like they know what they're talking about.

 

[megadrive0088]

there are three known / likely possibilities for amount of PEs. 4, 8 or 16.

the middle route seems the most likely to me. 8 PEs, thus 64 APUs. assuming 32 GFLOPs / per APU that gives us 1 TFLOPs @ 500 Mhz

At just 1 Ghz, that gives us 2 TFLOPs, if they manage 4 GHz, that's a stunning 8 TFLOPs. is that possible given the 65nm process?

even 2 Ghz would give us 4 TFLOPs.


now if they went with 16 PEs, with 8 APUs each, that's 128 APUs. @500 Mhz that is 2 TFLOPs, @1 Ghz that is 4 TFLOPs.


I think Sony will deliever Teraflops performance as they have said in the past. remember 1 TFLOP is PEAK performance and would never actually reach TFLOP level in practice.

 

[V3]

Are you sure? How strong is the coupling. Especially, in terms of accessing memory et al. If the cores are meant to communicate a lot -- which I'm pretty sure they will be -- they'll need good syncronisation unless they're using async communication like a lot of high performance MPUs these days.

They can sandbox memory, from the next BE chip if it is needed. They don't need to use eDRAM that's local to the chip. So you can imagine what kinda coupling it is going to have.

The APUs are on its own, the PU ochestrates them. Beside that, they have absolute timer, any skew probably compensated with that, if not compensated else where.

 

[-tkf-]

Late to the pary with these links?

http://www.excite.co.jp/world/url/b...C%96%F3&wb_lp=JAEN&wb_dis=2&wb_co=excitejapan

And :

http://nkcp.zive.net/kokoro/archives/001146.html

 

[Gubbi]

there are three known / likely possibilities for amount of PEs. 4, 8 or 16.

the middle route seems the most likely to me. 8 PEs, thus 64 APUs. assuming 32 GFLOPs / per APU that gives us 1 TFLOPs @ 500 Mhz

One APU will do 8 floating point operations per cycle (4 FMADDs), so @ 500MHz you get 4GFLOPS per APU.

But they will clock faster.

The question is then how many PE/APUs there'll on the chip. 4 PEs, each with 8 APUs yields 512GFLOPS (@ 2GHz)which is pretty damn good. Then there is the visualizer.

IMO! When somebodys marketing department states it will do 1TFLOPS, that is the guarateed-not-to-exceed speed, or in other words the aggregate throughput of the host system and the rasterizer (and everything else).

Cheers
Gubbi

 

[megadrive0088]

Spec of PS3's "CELL"
Hiroshige Goto is one of most famous specialist about emerging technology. Especially semiconductor related topics is his domain.

He wrote very, very impressive article about PS3's chip named "CELL" through reading patent paper unveiled recently.

後藤弘茂のWeekly海外ニュース

A prefered instance for deploying Cell processors is 4 data * 8 APU * 4 PE. As a result, 512 32bit floating point arithmetic and 512 32bit integer arithmetic per clock are processed simultaneously. In short word the number of clock on CELL is 1 Tera FLOPS.

Specification is following;
-32 sub processors on one chip
-256 processing units
-max 1024 32bit data calculation
-1 Tera FLOPS power
-the number of transistors is over 1B <---- !!!!
-outer memory is "Yellowstone" DRAM by Rambus
-chip-interconnect technology will be "Redwood" by Rambus
-"Emotion Engine", the core chipset of PS2, is integrated in one chip with "Graphics Synthesizer".

 

[qwerty2000]

that means if the cell could do 1024 in 1 ghz that means it could do at 4 ghz 4098 tflops. But is sony wants to put 512 glops in 1 ghz and sony wants to put 2 ghz we'll be seeing a 1024 tflops gpu that would be asoume is that a good possiblity

 

[megadrive0088]

well... if PS3 is not going to exceed 1 TFLOPs - then in practice, it will be a high GFLOPs machine. not quite the monster we would all like, but still powerful. about as much of a leap from PS2, as PS2 was from PS1.... however, the rasterizer features and overall system efficiency thanks to caches & eDRAM and other things could boost the overall realworld results. im sure Panajev would agree


then again Sony is probably holding back on the actual PS3 performance even though we know the core technology is Cell - Processing Elements - PowerPCs - APUs - etc.

In early 1995, Ken K. said (in a Next Generation interview) that PSX2 would bring 10 million polygons a second on .25 micron process. he exceeded that conciderably with the actual PS2.

The optimist would think Sony will deliever MORE than 1000x PS2 performance

 

[qwerty2000]

the cpu alone has over 1 tflops

 

[London Geezer]

IT'S pretty safe to say that PS3 WILL be a -AT LEAST- 1Tflop machine. Sony already gave that figure and they will reach that number, whatever happens.
what kinda worries me is that they might focus of that 1 Tflop figure and compromise, cutting down other aspects of the arcitecture in order to keep that 1Tflop figure. of course i might be very wrong, but at the end of the day, whatever power next gen consoles have, the manufacturers will have to compromise in order to keep the cost down to an acceptable figure. Consoles are still *just consoles* which will have to be sold at a decent price. and manufacturers will only be willing to lose a certain amount of money on them.
the next generation of consoles will of course be mighty powerful compared to what we have today, but rememebr that they will still be results of clever compromise between performance and cost.
a good balanced console wouldnt hurt for once....