Not CUDA software version, but CUDA compute capability
GK104, 106 and 107 are 3.0
GK110 and 208 are 3.5
GM107 and 108 are 5.0 (yes, they skipped 4)
GK104, 106 and 107 are 3.0
GK110 and 208 are 3.5
GM107 and 108 are 5.0 (yes, they skipped 4)
I think this is learning from the largely unnoticed Maxwell presentation slide-fail, where Kepler was being depicted as having 256 ALUs per SMX.
So, this green giant on the right with it's 2x 21x11-config is something very odd - IMO on purpose. The left side - given the coloring - should be represenative of current CPUs.
So, this green giant on the right with it's 2x 21x11-config is something very odd - IMO on purpose. The left side - given the coloring - should be represenative of current CPUs.
Remember, the GTC slide had no absolute values, but normalized ones to, from what it would appear, Tesla, hence SGEMM. For DGEMM, the chart would go to infinity from Fermi onward, making it quite moot as a show-off-point for future generations.
The very first slide of the GTC 2014 keynote has escaped comment so far. What could it mean?
A clue about hexacore Tegra 6?
6 Denver cores on big Maxwell?
The grids of green boxes don't jibe with either. Yet this slide is clearly presented on purpose. Please speculate!
Unified Memory in CUDA 6
https://devblogs.nvidia.com/parallelforall/wp-content/uploads/sites/3/2013/11/unified_memory.png
Hexacore Denver + 1056(?) Maxwell cores.The very first slide of the GTC 2014 keynote has escaped comment so far. What could it mean?
A clue about hexacore Tegra 6?
6 Denver cores on big Maxwell?
The grids of green boxes don't jibe with either. Yet this slide is clearly presented on purpose. Please speculate!
Perhaps this is using 16nm?
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Blazkowicz
Legend
It is an abstraction? You're not meant to count the squares or identify the blue chip with any real product.
Even the Tegra K1 "die shots" (both ARMv7 and ARMv8 versions) are artistic views.
Even the Tegra K1 "die shots" (both ARMv7 and ARMv8 versions) are artistic views.
firstminion
Newcomer
That's virtual, no? i.e. the driver handles the memory management.
LiXiangyang
Newcomer
Just bought a 860M notebook, without recompilation/changing any codes, in terms of efficiency (in terms of achieved flops/iops against theoetrical flops/iops etc) GM107 offer 10+% improvement over GK110.
And unlike Kepler, Maxwell's 32bit FMA can work at full speed.
And unlike Kepler, Maxwell's 32bit FMA can work at full speed.
http://techreport.com/review/26239/a-closer-look-at-directx-12
Looks like Intel Pixelsync needs to be supported in DX12 new hardware features.
Wonder if Maxwell supports it.
Looks like Intel Pixelsync needs to be supported in DX12 new hardware features.
Wonder if Maxwell supports it.
UniversalTruth
Veteran
Which manufacturing processes?
http://techreport.com/review/26239/a-closer-look-at-directx-12
Looks like Intel Pixelsync needs to be supported in DX12 new hardware features.
Wonder if Maxwell supports it.
Is Pixelsync anything but Intel's name for OIT, supported by Radeons since forever (HD5 I think it was)?
The DX12 feature is the pixel ordered UAV.
Pixelsync would be the name of the hardware feature that enables it for Intel, which in turn enables programmable blending and efficient OIT.
Pixelsync would be the name of the hardware feature that enables it for Intel, which in turn enables programmable blending and efficient OIT.
iMacmatician
Regular
From Sweclockers: "Nvidia Maxwell in 20 nanometers is delayed until 2015" (original).
Not terribly surprising to me if the high-end Maxwells are going to use 20 nm.
Not terribly surprising to me if the high-end Maxwells are going to use 20 nm.
UniversalTruth
Veteran
That is why Nvidia claimed 20nm was essentially worthless. Not only because of costs but because it would be replaced by a more advance process extremely quickly.
unless they start running into problems with 16nm. Wouldn't be the first ill fated process
