NVIDIA Maxwell Speculation Thread

[Kaotik]

Both Kepler and Maxwell supports CUDA 6, does not mean they are the same arch.

Not CUDA software version, but CUDA compute capability
GK104, 106 and 107 are 3.0
GK110 and 208 are 3.5
GM107 and 108 are 5.0 (yes, they skipped 4)

 

[spworley]

The very first slide of the GTC 2014 keynote has escaped comment so far. What could it mean?

A clue about hexacore Tegra 6?
6 Denver cores on big Maxwell?
The grids of green boxes don't jibe with either. Yet this slide is clearly presented on purpose. Please speculate!

 

[CarstenS]

I think this is learning from the largely unnoticed Maxwell presentation slide-fail, where Kepler was being depicted as having 256 ALUs per SMX.

So, this green giant on the right with it's 2x 21x11-config is something very odd - IMO on purpose. The left side - given the coloring - should be represenative of current CPUs.

 

[CarstenS]

Probably an error and it should be DGEMM/W. GK110 is >10 GFLOPs per watt @ SGEMM.

Remember, the GTC slide had no absolute values, but normalized ones to, from what it would appear, Tesla, hence SGEMM. For DGEMM, the chart would go to infinity from Fermi onward, making it quite moot as a show-off-point for future generations.

 

[itaru]

The very first slide of the GTC 2014 keynote has escaped comment so far. What could it mean?

A clue about hexacore Tegra 6?
6 Denver cores on big Maxwell?
The grids of green boxes don't jibe with either. Yet this slide is clearly presented on purpose. Please speculate!

Unified Memory in CUDA 6

https://devblogs.nvidia.com/parallelforall/wp-content/uploads/sites/3/2013/11/unified_memory.png

 

[Wynix]

The very first slide of the GTC 2014 keynote has escaped comment so far. What could it mean?

A clue about hexacore Tegra 6?
6 Denver cores on big Maxwell?
The grids of green boxes don't jibe with either. Yet this slide is clearly presented on purpose. Please speculate!

Hexacore Denver + 1056(?) Maxwell cores.
Perhaps this is using 16nm?

 

[Blazkowicz]

It is an abstraction? You're not meant to count the squares or identify the blue chip with any real product.

Even the Tegra K1 "die shots" (both ARMv7 and ARMv8 versions) are artistic views.

 

[itaru]

It is an abstraction? You're not meant to count the squares or identify the blue chip with any real product.

Even the Tegra K1 "die shots" (both ARMv7 and ARMv8 versions) are artistic views.

no
that is intel xeon

 

[lanek]

i really dont understant how you go so far ..

 

[firstminion]

Unified Memory in CUDA 6

https://devblogs.nvidia.com/parallelforall/wp-content/uploads/sites/3/2013/11/unified_memory.png

That's virtual, no? i.e. the driver handles the memory management.

 

[MfA]

That would make the response time to a page miss on the GPU rather long ... hopefully the GPU has it's own processor to act like a TLB and "cache" controller using something like ARC to migrate pages between system memory and the GPU.

 

[LiXiangyang]

Just bought a 860M notebook, without recompilation/changing any codes, in terms of efficiency (in terms of achieved flops/iops against theoetrical flops/iops etc) GM107 offer 10+% improvement over GK110.

And unlike Kepler, Maxwell's 32bit FMA can work at full speed.

 

[DSC]

http://techreport.com/review/26239/a-closer-look-at-directx-12

Looks like Intel Pixelsync needs to be supported in DX12 new hardware features.

Wonder if Maxwell supports it.

 

[UniversalTruth]

2nd Gen Maxwell will be out later this year. GM204 and GM206 are on track for a release towards late Q3/early Q4. The info I've heard is that GM204 is currently being taped out at TSMC and first silicon is expected back from the fab sometime next month. GM206 is slightly behind GM204 and there is a "big Maxwell" GM200 in the pipeline as well.

I noticed the change in graph as well. I think its just marketing. The graph from the old roadmap looked more linear, whereas the new one looks more exponential.

Nope, NV is not going to give up the "big chip" strategy just yet. As stated above, GM200 does exist and will be released as the last member of the family, just like the Kepler generation.

Which manufacturing processes?

 

[Kaotik]

http://techreport.com/review/26239/a-closer-look-at-directx-12

Looks like Intel Pixelsync needs to be supported in DX12 new hardware features.

Wonder if Maxwell supports it.

Is Pixelsync anything but Intel's name for OIT, supported by Radeons since forever (HD5 I think it was)?

 

[3dilettante]

The DX12 feature is the pixel ordered UAV.
Pixelsync would be the name of the hardware feature that enables it for Intel, which in turn enables programmable blending and efficient OIT.

 

[iMacmatician]

From Sweclockers: "Nvidia Maxwell in 20 nanometers is delayed until 2015" (original).

Not terribly surprising to me if the high-end Maxwells are going to use 20 nm.

 

[Wynix]

^ I hope that is an April Fool's joke.

 

[UniversalTruth]

That is why Nvidia claimed 20nm was essentially worthless. Not only because of costs but because it would be replaced by a more advance process extremely quickly.

 

[eastmen]

That is why Nvidia claimed 20nm was essentially worthless. Not only because of costs but because it would be replaced by a more advance process extremely quickly.

unless they start running into problems with 16nm. Wouldn't be the first ill fated process