Blazkowicz
Legend
It is like NV38 and NV48, not a real new chip but it's the top dog of the arch.
Also K40 product material was changed from GK180 to G110B. The DLL-entries should at least imply that there was some simulation done with this GPU.
It is easy to see that the big Maxwell can not be 28nm, nor is it likely that it will be the first chip on the process. If we believe GM2XX stands for die DX12 ready chip designs, the 2 tells us nothing about the process those chips will be made in, but it could mean that they needed some changes to the design, which means tape-out can only happen after DX12 specs went final, So maybe April or May at best. At 6 months from tape-out and you look at a Q4/14 release. By then 20nm SOC should be ready, so it makes sense to assume GM2XX will be 20nm.
Very unlikely that dx12 featurelevels will be fixed that soon (hw features are not the focus, and they are still just in first iteration of api design) and not very important that gm2xx expose all features of an api a year out in the future.. hell, gm10x doesn't even have the almost 2 years old featurelevel...
There's a HUGE difference between a process being "ready" (where I'd figure that capacities get more reasonable for 20SoC after this summer) and being "affordable" for a specific transistor budget. If you'd believe TSMC's marketing claims 20SoC is "ready" for months now.
GM200 could be the only other exception here, but there's no rush for them to release it immediately for desktop either, as professional markets could again absorbe the high manufacturing cost under 20SoC.
I could be wrong, but there's quite some time now I am aware of only ONE potential 20SoC bin for NV before this year runs out.
I know we have had the discussion of Second Generation Maxwell but is it likely say that the full use of the GM204 on 28nm would be able say to be good as the GK110 in single precision?
I've got a feeling that Maxwell won't be around as long as Kepler.
This is kind of why I'm sceptical if they'll be any 20nm Desktop/Notebook Maxwell; not much of a performance gain from 28nm HP, its too cost ineffective, by the time it becomes so then 16nmFF will likely be viable for Desktop/Notebook use and it'll just be better to get Pascal GPxx0/4/6 out of the door.
I've got a feeling that Maxwell won't be around as long as Kepler.
its absolutely not a problem for Nvidia to call they hardware DX12 compatible, even if there gpu's dont support it in hardware ( lets not forget there's different level of the API support, software, and hardware ).... Specially, as the hardware features is unknown right now, and DX12 as it is right now, look more like a rework of the actual DX11.2 + DX11 "Xbox one " mix ... Im not even sure they want rewrite Maxwell for support DX12 hardware support, when they are able to push Fermi, Kepler and actual Maxwell 750TI in the DX12 compatibility level . Today DX12 is just a change on how the API is communicate with the hardware... there's no need to change the hardware.
DX12 "FIRST" games will be out for the end of 2015... this dont mean thoses games will require DX12 hardware support features, but basically the rewrite of the API / codes .. Pascal will be out in the current of 2016 ( some month laters ), i dont see them release hardware features support before this one . ( some change in the design will take too much time for get maxwell out in 2015 )
I can be wrong, but for me, the delay of the next "20nm" architectures of AMD and Nvidia, is only due to the process.... something have push both companies to revisit their plan with the today architectures process, timing, and roadmap of their next arcthitectures ( and this is not DX12 ) ..
Its not an hasard if VI is not in 20nm, its not an hasard if first "maxwell" is not in 20nm and is a entry level gpu.. its not an hasard too if Nvidia have change his roadmap for Volta, and introduce Pascal in the between.
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Depends on the amount of SMMs; if they'd go for say 4x times the clusters as on GM107 based on past track record the result could be a healthy bit ahead of a GK110 in games.
And who says that 16FF is all that much better than 20SoC? 16 FinFET is nothing else but 20nm at TSMC with FinFETs and as already has been noted FinFET is more than just expensive for the moment. Count to that that it'll take some time for 16FF to mature at TSMC and them to start growing capacities for it I'd rather suggest that they might stay longer on 20SoC than many would expect.
That would mean that processes would magically become less problematic; reality would tell you that it's the exact opposite.
I have to agree with him, if the process is problematic and you're not able to squeeze out more performance because of it, you'll have to turn to other technologies like stacked memory which enable better performance regardless of process. If stacked memory becomes commercially viable, I can see NVIDIA taking advantage of that and quickly moving to an architecture that;s built around it.
I didn't mean they'd move to processes quickly, I think Nvidia is going to not immediately jump onto newer ones. Since TSMC 16nmFF is the same/similar to 20nm with the exception to FinFETS it'll probably be relatively cost effective to do in 2016 rather than a 20nm GPU late 2014/early 2015. I think Pascal will be on 16nm FF at the end of 2016 while TSMC is nearly ready to start mass producing 10nm and then wait for that process until 2018 with Volta.
Overall I did not mean that process shrinks would become easier but rather that Nvidia will "delay" process transitions, espeically their Desktop GPUs. I think we'll see their mobile chips going 20nm but not desktop ones.
If 20SoC won't help than 16FF won't help much either. Process technology has become increasingly problematic, else you don't get less problems but more as processes get smaller and cost rises and it takes longer and what else is new.
If any of you has a viable explanation why 16FF@TSMC is supposed to be the Messiah process or more than marginally better or less problematic than 20SoC I'm all eyes to read a couple of viable points instead of sterile gut feelings with no background knowledge.
The situation bears strong similarities to when Intel went to HiKMG at 45nm, while the foundries stayed with regular gate dielectrics until 32/28nm, leaving the 40nm range to suffer from significant leakage and variability problems at least early.
Everyone knew there were increasing problems with scaling where physical changes to the transistors were needed avoid getting smacked by physics.
Intel had the resources and financial incentive to make the jump early, and it benefited immensely.
The foundries didn't, and they got smacked.
Each material change to the transistor tech is more of a one-time reset that pushes the process a little ways back up the steep slope of diminishing returns, so to maintain scaling Intel went with FinFETs. There are new sources of variability with FinFETs, such as issues with uniformity of fin height and pitch. However, it provides much better performance and control over the transistor's switching, which is an area where bulk planar is showing serious problems.
The other process players are delaying, and they will have yet another node missing a tech needed to offset serious physical problems at those geometries.
AMD already stated as much when they stated why Steamroller stayed at 28nm, and the scaling numbers aren't great in the foundry marketing.
The hybrid nodes are pretty much 20nm with transistors that aren't at the borderline of being unacceptable.
Agreed.
Sounds reasonable too.
Then they have a problem; if they entirely skip 20SoC then they won't be able to get a GM200 into 28HP and they'll have to stay a mighty long time with whatever 28HP smaller Maxwell chips should appear in the meantime.
Tegra used to be:
Logan (Tegra K1) 28HPm
Parker 16 FinFET
...which seems now to be:
Logan (Tegra K1) 28HPm
Erista 20SoC?
Parker 16 FinFET
If anything it sounds more than anything but a delay for 16FF than anything else (under the presupposition that Erista & Parker are on the speculated process variants).
For a subset of clients, it may be.
There's still a density and time to market advantage, however.
If a design is okay with middling performance scaling and it is disciplined enough with power consumption, being able to get more hardware into a design whose die size is constrained for other reasons might help.
This is probably more critical in the mobile SOC space and a few other spaces where the features and hardware arms race is ongoing.
A somewhat more expensive chip may be better in the face of serious competition whose features/blue crystals gut the prices of existing inventory.
The entire point of the finfet transistors is to improve the performance and power, especially leakage, over the traditional transistors. The process should really be called 20FF, not 16FF because I think density will not be much better.
That's all fine and dandy, but FinFET transistors are going to be also quite a bit more expensive and not 16FF is not remotely close for prime time not even in H1 15' it seems.
By the way when was it the last time NV was intensively bickering again about a process at TSMC? Wasn't it 40G?
40 and 28nm.
Though to be fair, 28nm bickering was probably due to their reluctance to sign a long term contract with TSMC.
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