NVIDIA GF100 & Friends speculation

[Kaotik]

Why would they bother blacking out the PCI-e interface and power plugs? Do they have a "Super PCI-e" interface with 3x the checkmarks that is under NDA?

It's not uncommon to have logos really close to PCIe interface

 

[ShaidarHaran]

Why would they bother blacking out the PCI-e interface and power plugs? Do they have a "Super PCI-e" interface with 3x the checkmarks that is under NDA?

I dunno about NV, but IIRC ATi usually prints a part number or some similar identifying marker on the PCB in the area of the PCI-e connector. As for the PCI-e power connectors being blacked out, they were probably trying to hide how many pins each connector has, but you can still see the standoff pins which clearly indicate an 8 pin and a 6 pin.

 

[swaaye]

AMD obviously made allowances and built the best product they could build with what they could get from TSMC. Nvidia didn't make any compromises, and ended up with something that couldn't be built on TSMC's process for the first year. Now ATI has had a clear run with better yeilds, and Nvidia are running around trying to do another re-spin and doing a small-run PE launch with a compromised product that may be outdated by the next-gen from ATI almost as soon as it arrives.

ATI said this kind of thing back when they built R300 on 150nm instead of 130nm and the 130nm NV30 didn't work out so well. That didn't stop them from screwing up a few generations down the road though, including the biggest mess up of them all perhaps in R600.

We still don't know exactly how Fermi is going to turn out. I'm ignoring the rumor mill at this point and just waiting to see the benches and the availability for myself. Obviously it's been troublesome, but if it had worked out better ATI's relatively small RV870 could have been in big trouble. There's risk in everything, eh?

 

[Malo]

It's not uncommon to have logos really close to PCIe interface

I dunno about NV, but IIRC ATi usually prints a part number or some similar identifying marker on the PCB in the area of the PCI-e connector.

ah ok, thanks guys. Figured there would be a sensible reason.

 

[trinibwoy]

"According to company sources, the final specifications for the GTX-480-chip will have yet. Unconfirmed rumors that the GeForce GTX 480 is not even the previously assumed number of 512 shader cores have, but something less."

Is that a new rumor? Or have I missed something?

It's not new and my money is on a 480 shader GTX 480. Razor, the number of enabled SM's has nothing to do with the memory bus-width.

 

[Arty]

Maybe S/A was too optimistic with their prediction of 8000-10000 cards. Tweaker.net says 5000 worldwide at launch.

Ok, it looks like conflicting reports intentionally being pumped by NV. We have the regular suspects claiming limited availability on one hand while Rys is being led to believe that its the opposite .. in the end bridges will be burned.

edit: For what its worth (ZERO), Theo also claimed 550mm2+ from his sources.

It's not new and my money is on a 480 shader GTX 480. Razor, the number of enabled SM's has nothing to do with the memory bus-width.

Coincidence? 480 shaders for the GTX 480.

 

[Kaotik]

Coincidence? 480 shaders for the GTX 480.

Nah, it's just the smallest step they can go down

 

[FenderBender]

Metal spins are used to fix functional bugs. I can't call a chip which needs a metal spin to work as a "working" chip. If by production quality you mean yields, power and clocks, then they need a silicon respin to fix.

Slightly offtopic request, but what's a good source to learn the basics of chip design production? Something that would talk about the function of different layers (why is only metal functional? How does a new spin allow you to adjust speeds or power or reduce defects? How are hot lots used and scheduled? What process tweaks would make transistors less leaky? ) Google tends to find either deep technical papers or light breezy : "a fab makes computer chips from silicon, using a tiny slide projector to print the little transistors!"

I just keep hearing things like "metal spins fix functional bugs" and I want to spend an a day to learn more about how the process works at that kind of engineering pipeline level.

A deep tech summary online would be great, but even a textbook would be worth investing in because it's so interesting.

 

[Rys]

We have the regular suspects claiming limited availability on one hand while Rys is being led to believe that its the opposite .. in the end bridges will be burned.

I'm only talking about review hardware availability, not retail.

 

[RecessionCone]

Slightly offtopic request, but what's a good source to learn the basics of chip design production? Something that would talk about the function of different layers (why is only metal functional? How does a new spin allow you to adjust speeds or power or reduce defects? How are hot lots used and scheduled? What process tweaks would make transistors less leaky? ) Google tends to find either deep technical papers or light breezy : "a fab makes computer chips from silicon, using a tiny slide projector to print the little transistors!"

I just keep hearing things like "metal spins fix functional bugs" and I want to spend an a day to learn more about how the process works at that kind of engineering pipeline level.

A deep tech summary online would be great, but even a textbook would be worth investing in because it's so interesting.

It's not true that metal spins fix functional bugs only, that's an oversimplification. The base silicon layers form the transistors, the fundamental switches that make up a chip. It takes many steps to print the transistors, since the silicon has to be doped in different ways for the N & P transistors, the gates of the transistors have to be laid using polysilicon, etc. In contrast, forming the metal layers is relatively simple. For each layer, you just record where the wires are, and where the connections are to other layers (vias). Usually the metal layers alternate in directions, with each layer having either north-south wires or east-west wires, and usually the size of each wire on a given layer is fixed (unlike transistors, which need to be built in many sizes).

Since designing and printing the wires is so much simpler than designing and printing the transistors, companies try to fix their chips by just changing the wiring (a metal spin), keeping the transistors in exactly the same places and sizes as before. Sometimes the design has a bunch of extra, unused transistors lying around just in case a functional bug is discovered, then a metal spin can change the connections to use the extra transistors and fix the bug. But you can use metal spins to fix yield, power and timing issues as well: for example, if the vias are often defective (as Nvidia has complained about TSMC's 40 nm process), you can add redundant vias with a metal spin. Also, since the electrical properties of circuits on a chip these days are often limited by the wiring, you can affect the timing and power consumption of a circuit by changing only the metal, although there are obviously diminishing returns.

 

[aaronspink]

Slightly offtopic request, but what's a good source to learn the basics of chip design production? Something that would talk about the function of different layers (why is only metal functional? How does a new spin allow you to adjust speeds or power or reduce defects? How are hot lots used and scheduled? What process tweaks would make transistors less leaky? ) Google tends to find either deep technical papers or light breezy : "a fab makes computer chips from silicon, using a tiny slide projector to print the little transistors!"

I just keep hearing things like "metal spins fix functional bugs" and I want to spend an a day to learn more about how the process works at that kind of engineering pipeline level.

A deep tech summary online would be great, but even a textbook would be worth investing in because it's so interesting.

College is your best bet . Outside of that, you might be able to find course presentations/etc for a VLSI design class online somewhere. For University of Michigan it would be EECS427. Don't know about other schools.

 

[RecessionCone]

College is your best bet . Outside of that, you might be able to find course presentations/etc for a VLIW design class online somewhere. For University of Michigan it would be EECS427. Don't know about other schools.

I'm sure this is inadvertent, but VLSI is the right acronym, not VLIW.

 

[FenderBender]

RecessionCone: excellent, super clear info, thanks very much!

What do the layers above metal do, then? Is it right that A1 A2 A3 spins don't affect the metal, and in theory a B1 spin would be a metal change?

Why is it harder to do a full respin and move/change the base transistors as well? Do those transistor layers take longer to make masks for, or is it because they already have lots of wafers with printed transistors but no metal yet and they don't want to waste those wafers?


And, going back to NVIDIA, has NV in the past done respins after launch and silently "upgraded" shipping parts with lower power? G200b was a full process shrink, and NV (mostly) changed model numbers to show the difference (280 became 285, new 275 introduced, but 260 was just upgraded)

For example, if you buy a GTX480 on launch day, is it possible the GTX480 you buy 6 months later is a different spin and may use less wattage even with identical clocks and specs?

 

[Razor1]

RecessionCone: excellent, super clear info, thanks very much!

What do the layers above metal do, then? Is it right that A1 A2 A3 spins don't affect the metal, and in theory a B1 spin would be a metal change?

Why is it harder to do a full respin and move/change the base transistors as well? Do those transistor layers take longer to make masks for, or is it because they already have lots of wafers with printed transistors but no metal yet and they don't want to waste those wafers?


And, going back to NVIDIA, has NV in the past done respins after launch and silently "upgraded" shipping parts with lower power? G200b was a full process shrink, and NV (mostly) changed model numbers to show the difference (280 became 285, new 275 introduced, but 260 was just upgraded)

For example, if you buy a GTX480 on launch day, is it possible the GTX480 you buy 6 months later is a different spin and may use less wattage even with identical clocks and specs?

anything Ax is a metal respin anything Bx is a silicon respin, a silicon respin (full respin) will require new metal layers, also depending on which metal has to be respun that will effect the other layers as well, this is why when a lot is parked, it might save time later on.

Yes in the past nV has substituted a respin as time went down the road but also used respins for refreshes as well.

 

[Arty]

I'm only talking about review hardware availability, not retail.

Gotcha.

So the the only conflicting bit (I'll take Rys' word on this) is the die size.

 

[Alexko]

It's not true that metal spins fix functional bugs only, that's an oversimplification. The base silicon layers form the transistors, the fundamental switches that make up a chip. It takes many steps to print the transistors, since the silicon has to be doped in different ways for the N & P transistors, the gates of the transistors have to be laid using polysilicon, etc. In contrast, forming the metal layers is relatively simple. For each layer, you just record where the wires are, and where the connections are to other layers (vias). Usually the metal layers alternate in directions, with each layer having either north-south wires or east-west wires, and usually the size of each wire on a given layer is fixed (unlike transistors, which need to be built in many sizes).

Since designing and printing the wires is so much simpler than designing and printing the transistors, companies try to fix their chips by just changing the wiring (a metal spin), keeping the transistors in exactly the same places and sizes as before. Sometimes the design has a bunch of extra, unused transistors lying around just in case a functional bug is discovered, then a metal spin can change the connections to use the extra transistors and fix the bug. But you can use metal spins to fix yield, power and timing issues as well: for example, if the vias are often defective (as Nvidia has complained about TSMC's 40 nm process), you can add redundant vias with a metal spin. Also, since the electrical properties of circuits on a chip these days are often limited by the wiring, you can affect the timing and power consumption of a circuit by changing only the metal, although there are obviously diminishing returns.

That was quite instructive, thanks for taking the time!

I'm not entirely clear on the bold part, though. What do you mean by "the electrical properties of circuits are often limited by the wiring"?

 

[Dave Baumann]

Also, since the electrical properties of circuits on a chip these days are often limited by the wiring, you can affect the timing and power consumption of a circuit by changing only the metal, although there are obviously diminishing returns.

Yup. I had two SIMD's on RV770 that were mysteriously signifcantly slower than the rest, at the time we had the options of limiting the upper clock or dropping those two SIMD's entirely. Even though this wasn't considered as a gate to A12 the engineering team spent days and nights in the run up to the spin invesigating it and adding buffers in the metal layers to help the timing. Fortunatly it worked, and in fact A12 came back even faster than A11 with those two SIMD's disabled.

 

[aaronspink]

RecessionCone: excellent, super clear info, thanks very much!

What do the layers above metal do, then? Is it right that A1 A2 A3 spins don't affect the metal, and in theory a B1 spin would be a metal change?

No layers above metal. Its goes:

Transistors Channels/gate
"poly" though poly generally isn't poly anymore.
Metal 1
Metal 2
...
Metal X
Passivization layer (basically a protective/sealing layer)

With the transistors being the lowest and Metal X being the highest.

Why is it harder to do a full respin and move/change the base transistors as well? Do those transistor layers take longer to make masks for, or is it because they already have lots of wafers with printed transistors but no metal yet and they don't want to waste those wafers?

not harder, just more time consuming. Its all built up like a layer or wedding cake, once the lower layers are on, you can't change them.

 

[Davros]

Dave, About your sig what part of the 5800 did I design ?

 

[aaronspink]

Yup. I had two SIMD's on RV770 that were mysteriously signifcantly slower than the rest, at the time we had the options of limiting the upper clock or dropping those two SIMD's entirely. Even though this wasn't considered as a gate to A12 the engineering team spent days and nights in the run up to the spin invesigating it and adding buffers in the metal layers to help the timing. Fortunatly it worked, and in fact A12 came back even faster than A11 with those two SIMD's disabled.

Well they couldn't have added buffers in the metal layers. They could of reworked the metal layers to patch in some bonus buffers/inverters that were already on the silicon or they could of increased the width/shielding of the metal.