No, that slide recaps all the features talked about publicly. Just as much noise was made about SSD, RT, and 3D Audio.I don't call that vocal..just a "feature" with no details. They emphasised other topics far more.
No, that slide recaps all the features talked about publicly. Just as much noise was made about SSD, RT, and 3D Audio.I don't call that vocal..just a "feature" with no details. They emphasised other topics far more.
No, that slide recaps all the features talked about publicly. Just as much noise was made about SSD, RT, and 3D Audio.
Wow a caseless console....They haven't even shown or talked about the case. Are we sure they even have one? We know they have a logo because they showcased that.
/s
They prefer See Thru Console. Kinda like the current dress fashion.Wow a caseless console....
Apparently only intelligent people can see if. If you haven't seen it...well...but I have. It's amazing looking. Really...er...good looking console, 'coz I'm smart.They haven't even shown or talked about the case. Are we sure they even have one? We know they have a logo because they showcased that.
I believe you mean Artificially intelligent, AI is everywhere these days in gaming.Apparently only intelligent people can see if. If you haven't seen it...well...but I have. It's amazing looking. Really...er...good looking console, 'coz I'm smart.
The slide is from an AMD presentation:
https://www.tomshardware.com/news/a...noa-architecture-microarchitecture,40561.html
Btw, does the shared cache automatically mean 8-core CCX or are the other factors that make up the cluster?
How can u not consider the L3? It’s the L3 that connects the CCX cores together. Or am I wrong?
I thought cores within the CCX pass data to each other through the L3 while data is passed to other CCXs using infinity fabric.
If 8 cores share a L3 and each with its own L3 slice, how would it not be an CCX?
Sorry perhaps i wasn't clear enough.
I totally agree with everything you said, considering the L3 as part of the core makes sense.
I was just allowing for the possability of some crazy setup, unrelated to Zen, where by you might have a CCX like configuration but not determined by the L3.
EG. if the L3 was a pure victim cache, and maybe the memory controller sat between the L2, and L3 you could have a huge combined L3, which could in theory be faster than DRAM in case of a L3 hit,
but it would be pseduo independent of the ccx size, as multiple ccx's could possibly share a single L3 victim cache...
But i think we are getting waaaaay off topic here
A more useful / valuable discussion would be to theorize on the way-ness and latency of the new combined 32Mb L3,
currently the 16MB L2 is 16 way, ~~ 40cycle, what cost does moving to a 32MB L3 come at? 32 way, @ 50cycles? 50 cycles is a looong wait...
But agian, this is not related at all to Next-gen consoles... maybe i'll float it in the Zen3 thread
Generally more clock speed is easier to scale, as the whole pipeline improves together. So whatever bottlenecks you had will continue, making mitigation easier to resolve.Have we discussed the possible BOM of two different design approaches?
That is, "narrow and fast " vs. "wide and slow" if the performance is very close.
For example, given xbox has 60~64CUs with 56CUs enabled @ 1.67GHz (12TF), some analysts already predict $460~520 BOM
Since some reports suggest the cooling solution may be relatively cheap, if SONY chooses something like
48CUs with 44CUs active @ 1.96GHz (11TF) with better cooling solution, do we have any idea how much difference of BOM will be?
$20? or $50 ?
What will be the actual performance difference between a 11TF high-frequency GPU and 12TF lower-frequency GPU?
Powerwise wide and slow should scale better though?Generally more clock speed is easier to scale, as the whole pipeline improves together. So whatever bottlenecks you had will continue, making mitigation easier to resolve.
With wide and slow, you really have to watch where new bottlenecks could show up.
yes lol at the cost of die size.Powerwise wide and slow should scale better though?
However if cooling solution is really only several dollars (or relatively cheap) then power consumption may not be a major concern of BOM and the "narrow and fast " console may achieve lower BOM with roughly the same performance.Powerwise wide and slow should scale better though?
Consoles should at least have the benefit of having both CCXs, all IF traffic and the memory controller all on the same die.
That should, in theory, allow for reduced latencies and potentially a small gain in throughput.
I'm looking forward to seeing the 4xxx series APUs getting examined by the likes of Anandtech, especially if the consoles are going to have similarly reduced L3 caches.