Next Generation Hardware Speculation with a Technical Spin [post E3 2019, pre GDC 2020] [XBSX, PS5]

Discussion in 'Console Technology' started by DavidGraham, Jun 9, 2019.

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  1. Pinstripe

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    I think Microsoft wants to omit the specs for now and give later Digital Foundry the honors for a detailed breakdown. The average consumer mustn't be confused with TFLOPS and RDNA and IPC and other nerdy abbreviations.
     
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  2. szymku

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    I think that a year from now anything is possible i.e. 12TF console in small form factor.By the time next gen hit the shelves there probably will be 18 TF NVidia cards available.
     
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  3. mpg1

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    You can hold the cards close to your chest while not adding fuel to rumoured numbers. Which is what Spencer kinda did with "2X Scorpio GPU power" and 12 already being out there.

    I think if you know that number is out there and the new console is not that number....then you are much more clearer in language in describing. Actually I'm kinda interested in when that Gamespot interview with Phil was done now. Was it before or after the Windows Central article with the leaked numbers. If it was before there would be less of a reason to be clear.
     
  4. Shortbread

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    I hope all of you guys are right…truly I do. However, my cynicism is grounded in years of console PR (hyperbole) and the current wattage/TDP constraints within a small form factor on reaching RTX 2080/Ti levels of performance.

    Like I said, I truly hope the PC space receives AMD’s magic for much more efficient GPUs producing equal or greater performance than Nvidia’s RTX product line. But we shall see...
     
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  5. mpg1

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    My cycinicism is less on the general power and more on AMD's hardware for ray tracing. Who knows if that will even work..
     
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  6. temesgen

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    I think TF is perhaps a less relevant measure than say 4k at 60fps with ray tracing. The memory set up and other modernization frankly interest me more. I'm hoping we see the CPU power used to up the simulation quality for AI and perhaps some procedural changes to assets so everything doesn't look the same.
     
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  7. Shortbread

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    Which DF mentioned as well.
     
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  8. mpg1

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  9. DavidGraham

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    Yeah, but they used a wider GPU, clocked it low @1200MHz to stay within the good efficiency range of GCN and still ended up with a 100w increase in power consumption compared to Xbox One S. Granted that difference includes the higher clocked CPU + GDDR5 + the new GPU, but you can bet most of that difference is due to the new GPU.

    So apparently that voltage tweaking didn't amount to much significant power savings, certainly not to the extent that enables a huge GPU die to fit within the expected power constraints of a home console.
     
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  10. Janne Kylliö

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    One thing to notice is how MS is describing the Xbox Series X APU using the same exact term AMD has used for post-Navi RDNA2 architecture:

    https://news.xbox.com/en-us/2019/12/12/microsoft-unveils-xbox-series-x/

    To me this implies that MS is using the yet publicly unnamed RDNA2 architecture and not Navi (RDNA1). And it also implies they are using the 7nm+ EUV process to manufacture the chips.

    Sony (or AMD for them) on the other hand has explicitly announced that they are using 7nm process and Navi architecture.

    So MS might have an upper hand here by using newer arch and more advanced process.
     
  11. PSman1700

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    This. God knows it's a 2080Ti in there, 13.4TF of full turing power with all it's advanced features. Devkits where containing 2080 series afterall. Just kidding offcourse not the baseless section :)
    But i agree, 12TF in the consoles means 16+ TF of rdna2 power, prompting nv to drop the high prices.
     
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  12. PSman1700

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    This isn't the baseless section.
     
  13. iroboto

    iroboto Daft Funk
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    It belongs here. It's not a baseless rumor with absolutely no technical underpinnings. The point of the two threads isn't (verified) talk in here (unverified) talk in there.

    It's whether you want to talk shop (here) or not talk shop (there)

    the quote in question
    I would also interpret this as being not RDNA 1. But coined as next generation RDNA since AMD has yet to name it.
     
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  14. Jay

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    Couple points.
    1. MS has already said its Navi based.
    2. RDNA2 could also fall under the branding Navi.

    So nothing to indicate that PS5 and XSX aren't based on the same RDNA base. Nothing to say either way.
     
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  15. PSman1700

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    I really thought he ment RDNA3.0, so i agree then.
     
  16. MrFox

    MrFox Deludedly Fantastic
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    As far as I'm concerned, everything changed when Xb SeX was unveiled. The engineers being allowed to use a 6" x 6" cross section is a massive advantage compared to anything that must be restrained to 2"-3" thick. Altough it's been done before with the SGI toaster (the O2), the Mac trashcan, and some recent PC cases.

    I wouldn't be surprised to see something around 250W here, and I fear the sony engineers will now feel empowered to ask the management to relax the traditional form factor requirement, since they can point out MS did it. There's still some hope they can have their cake and eat it too, I often proposed a 3" high box with two counter-rotating blower fans, very wide heatsink, and a very slim drive. It would cost more though. And it's much easier to be an armchair designer than making something that can be mass produced.
     
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  17. iroboto

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    According to the claims in the MS patent and looking at the requirement for VRS in DX12. I believe that the one MS has patented is their way of doing Tier 2 (if I am reading correctly). I've highlighted what I believe are the major differences for spotting.

    From reading AMD patent, I believe it designed so far to only support Tier 1.

    Turing's VRS method supports portions of Tier 2. I'm am unsure if it's full Tier 2 support.

    My current understanding:
    MS' method has multiple methods in which developers can determine the sampling method in determine how to shade the sampled area. Ranging from directly inputed values, to texture, SSR, vertices, it has a range of methods to determine the regions in which the shading rate is determined in a single draw call.

    Turing provides a couple methods too; though without seeing the patent, from their website it appears to support from a variety of methods as well; though not all the methods that MS has.

    AMD's patent showcases heavy usage of quads to determine it's shading rates; I believe this is inferior to the other methods, as the image is tiled and put into fine grain quads. So it doesn't seem to support textures or vertices. Nor does it appear to accept just provided sampling value either. I suspect if you have a bunch of angled items that you want variably shaded differently from the rest, then this is not going to be as effective here. I think a drawback here for AMD's method is going to be clarity around the edges.


    ***
    VRS Abstract MS:
    Methods and devices for rendering graphics in a computer system include a graphical processing unit (GPU) with a flexible, dynamic, application-directed mechanism for varying the rate at which fragment shading is performed for rendering an image to a display. In particular, the described aspects allow different shading rates to be used for different regions of a primitive based on a new, interpolated shading rate parameter. In other words, the described aspects enable the GPU to change shading rates on-the-fly between different fragments of each primitive. Additionally, or independently, the GPU utilizes each respective shading rate parameter to determine how many sample positions to consider to be covered by the computed shaded output, e.g., the fragment color, thereby allowing the color sample to be shared across two or more pixels.

    VRS Abstract AMD:
    A technique for performing rasterization and pixel shading with decoupled resolution is provided herein. The technique involves performing rasterization as normal to generate fine rasterization data and a set of (fine) quads. The quads are accumulated into a tile buffer and coarse quads are generated from the quads in the tile buffer based on a shading rate. The shading rate determines how many pixels of the fine quads are combined to generate coarse pixels of the coarse quads. Combination of fine pixels involves generating a single coarse pixel for each such fine pixel to be combined. The positions of the coarse pixels of the coarse quads are set based on the positions of the corresponding fine pixels. The coarse quads are shaded normally and the resulting shaded coarse quads are modified based on the fine rasterization data to generate shaded fine quads.

    As per Direct X specifications:
    edit: i guess we don't allow tables here

    Tier 1

    • Shading rate can only be specified on a per-draw-basis; nothing more granular than that
    • Shading rate applies uniformly to what is drawn independently of where it lies within the rendertarget
    • Use of 1x2, programmable sample positions, or conservative rasterization may cause fall-back into fine shading
    Tier 2
    • Shading rate can be specified on a per-draw-basis, as in Tier 1. It can also be specified by a combination of per-draw-basis, and of:
      • Semantic from the per-provoking-vertex, and
      • a screenspace image
    • Shading rates from the three sources are combined using a set of combiners
    • Screen space image tile size is 16x16 or smaller
    • Shading rate requested by the app is guaranteed to be delivered exactly (for precision of temporal and other reconstruction filters)
    • SV_ShadingRate PS input is supported
    • The per-provoking vertex rate, also referred to here as a per-primitive rate, is valid when one viewport is used and SV_ViewportIndex is not written to.
    • The per-provoking vertex rate, also referred to as a per-primitive rate, can be used with more than one viewport if the SupportsPerVertexShadingRateWithMultipleViewports cap is marked true. Additionally, in that case, it can be used when SV_ViewportIndex is written to.
    There's more:
    https://microsoft.github.io/DirectX-Specs/d3d/VariableRateShading.html

    Just going through this now. will edit for better reading in a moment. and I have some thoughts to write about.
    AMD patent: http://www.freepatentsonline.com/y2019/0066371.html
    MS patent: https://patents.google.com/patent/US20180047203A1/en
     
    #1997 iroboto, Dec 14, 2019
    Last edited: Dec 14, 2019
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  18. anexanhume

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    This “low” frequency was around a third higher than OG consoles launched at and nearly twice as wide. Also 20% faster than pro despite being on same node. It was still fairly aggressive.
     
    #1998 anexanhume, Dec 14, 2019
    Last edited: Dec 14, 2019
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  19. Proelite

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    Leaked Flute benchmarks showed 530GB/s effective bandwidth. 16 18gbps GDDR6 chips on 256bit bus. It's pretty much maxed out.
     
  20. ultragpu

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    That's disappointing, especially from the lads who gave us that 8 GB GDDR5 shocker haha.
     
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