Communication between cores and special logic goes through the ring.
It's possible the texture logic blocks are distributed along the ring, which would help with congestion.
The diagrams are too abstract to give any real indication, but if the chip were implemented as they were drawn, the ring would be a limiting factor.
Even if they are distributed, 32 filtered pixels per clock could conceivably be enough to saturate the bus.
It's possible the texture logic blocks are distributed along the ring, which would help with congestion.
The diagrams are too abstract to give any real indication, but if the chip were implemented as they were drawn, the ring would be a limiting factor.
Even if they are distributed, 32 filtered pixels per clock could conceivably be enough to saturate the bus.