Details trickle out on CELL processor...
- Thread starter j^aws
- Start date
NY Times article (not much info)
My bad...ISSCC is not in progress! 
It must've been a phantom/virtual one in my head!
http://www.nytimes.com/2004/11/29/t...39fd80203e&ei=5006&partner=ALTAVISTA1
The above link seems to work without registration...
I wanna see the software dammitt!
It must've been a phantom/virtual one in my head! one said:
http://www.nytimes.com/2004/11/29/t...39fd80203e&ei=5006&partner=ALTAVISTA1
The above link seems to work without registration...
I wanna see the software dammitt!
The CELL related 5 programs @ ISSCC 2005 -
10.2 The Design Implementation of a First-Generation CELL Processor
This is the main overview program.
7.4 A Streaming Processing Unit for a CELL Processor
26.7 A 4.8GHz Fully Pipelined Embedded SRAM in the Streaming Processor of a CELL Processor
These are for streaming processors.
20.3 A Double-Precision Multiplier for a First-Generation CELL Processor
This is by IBM,
28.9 Clocking and Circuit Design for a Parallel I/O on a First-Generation CELL Processor
and this is by Rambus, Inc. & Stanford University.
Note that all programs are supposed to describe First-Generation CELL Processor, which were already in production early this year. ISSCC doesn't adopt armchair theories, but actual samples.
10.2 The Design Implementation of a First-Generation CELL Processor
This is the main overview program.
7.4 A Streaming Processing Unit for a CELL Processor
26.7 A 4.8GHz Fully Pipelined Embedded SRAM in the Streaming Processor of a CELL Processor
These are for streaming processors.
20.3 A Double-Precision Multiplier for a First-Generation CELL Processor
This is by IBM,
28.9 Clocking and Circuit Design for a Parallel I/O on a First-Generation CELL Processor
and this is by Rambus, Inc. & Stanford University.
Note that all programs are supposed to describe First-Generation CELL Processor, which were already in production early this year. ISSCC doesn't adopt armchair theories, but actual samples.
one said:
Cool, so I'd assume we can say with reasonable probability that the first generation parts are based off the 10S, 90nm sSOI, process. Which would bode well indeed based off the speeds attained if they scale as expected to 65nm. Oh, and thanks for the round-up One.
EDIT: Nevermind, it states as much on the first page. Sorry for the useless post.
Isn't this on the basis of constantly using data that isn't cached in memory. It's probably worst case, for data that can be cached on chip the number would be higher, I guess the performance will hinge on how much onchip cache memory cell's have. I'm suspecting it won't be huge, so for large data sets which is what lot of next gen games will be using, the memory bandwidth may hinder a lot of the potential performance of the cell units. I guess we'll see if the 128k is enough. I guess it could all just be another case of sony concentrating on theoretical numbers instead of balancing the chip for maximum real world performance.
No, it's based on doing exactly one Floating point operation for every data read/write, which is much more extreme then simply not hitting the cache often. Even a cpu with no local memory or cache should easily beat that number with a reasonably sized register set.
Case in point - applying this logic to current Xenon specs, you top the machine out at 6.2GFlops...
The memory hierarchy is configured differently on a Stream processor. Multimedia applications don't run well on standard cache configurations like an x86 CPU.
http://cva.stanford.edu/imagine/project/im_overview.html
http://cva.stanford.edu/imagine/project/im_overview.html
FatherJohn
Newcomer
Now we still don't know if Sony's going to put 1 cell, 2 cells, or 4 cells in the PS3.
Comparing apples to pears:
One Cell seems very roughy in the same ballpark as an Xbox 2. (Especially if you think the GHz numbers end up converging, which is likely because both companies are buying their CPU technology from the same vendor.)
Sony seems to have a tough choice to make: launch at the same time as Xbox 2, but roughly at performance parity, or ride Moore's Law for one or two extra generations to get a more powerful product.
It looks like they're planning on waiting one year, which is 2/3rds of a Moore's Law cycle. That would tend to indicate that the PS3 will be a 2 Cell system. (And would tend to indicate that PS 3 will be 2 to 3 times more powerful than Xbox 2.)[/code]
Comparing apples to pears:
Code:
Item 1 cell Xbox 2
CPUs 1 @4.8GHz 3 @3.5+GHz
ALUs 8 @4.8GHz 48 @500+MHZ
On-CPU RAM 128K*8 = 1MB 1 MBOne Cell seems very roughy in the same ballpark as an Xbox 2. (Especially if you think the GHz numbers end up converging, which is likely because both companies are buying their CPU technology from the same vendor.)
Sony seems to have a tough choice to make: launch at the same time as Xbox 2, but roughly at performance parity, or ride Moore's Law for one or two extra generations to get a more powerful product.
It looks like they're planning on waiting one year, which is 2/3rds of a Moore's Law cycle. That would tend to indicate that the PS3 will be a 2 Cell system. (And would tend to indicate that PS 3 will be 2 to 3 times more powerful than Xbox 2.)[/code]
FatherJohn said:
Why would they wait? Most importantly, we don't know the area of one of these 90nm fabbed PE's yet, so we can't make a prediction for a yeildable 65nm IC. And, secondly, they have already been sampling 65nm, 2nd generation ICs; so whatever will end up in the PS3 likely exists already. The ones being discussed here have been around for around for awhile. And I also have my reasons to think the GHz won't converge, namely I believe there are architectural features that make Cell inheriently faster. And word on the street recently is that synthesis and placement is basically fucked for 65nm at IBM; as I told nAo, I see this as hurting the XCPU project more than Cell.
PS. You just compared a single Cell Processor to the entire X2 system and called that parity. Do you think the PS3 won't have a "GPU"? Think about it.
FatherJohn
Newcomer
Yeah, I don't think PS3 will have a full GPU. There's certainly no reason to have any vertex processors. And depending on how the second cell's APUs are configured they may be able to use them as some sort of renderer. (The Stanford Imagine group tried an experiment where they configured their stream processor as a Reyes-style renderer. It worked, but it was abysmally slow -- 20 time slower than a contemporary Z-buffer-based renderer, but using 3x the transistors. The dirty secret of stream-based processors is that they are very hard to get useful work out of.)
Sony's a fine company, but they can't magicly put more transistors into their products for the same price than other people can. So they are limited in what they can do. They have to make engineering trade offs, the same as their competitors.
They've chosen to invest heavily in APUs, and there isn't any practical use for APUs in a game machine other than rendering. So I assume that's what they're there for.
(People can wave their hands and say that the extra compute power is for physics or AI, or brand new uses that nobody's thought of yet. But I think that's pure wishful thinking. It's a waste of money to put in so much extra power unless most games can take advantage of it.)
Sony's a fine company, but they can't magicly put more transistors into their products for the same price than other people can. So they are limited in what they can do. They have to make engineering trade offs, the same as their competitors.
They've chosen to invest heavily in APUs, and there isn't any practical use for APUs in a game machine other than rendering. So I assume that's what they're there for.
(People can wave their hands and say that the extra compute power is for physics or AI, or brand new uses that nobody's thought of yet. But I think that's pure wishful thinking. It's a waste of money to put in so much extra power unless most games can take advantage of it.)
http://pc.watch.impress.co.jp/docs/2004/1129/cell.htm
A prototype Cell workstation by Sony/SCE/IBM is already up and running, its estimated performance is 16TFlops @ 1 rack. Now how many Cell does it contain?
A prototype Cell workstation by Sony/SCE/IBM is already up and running, its estimated performance is 16TFlops @ 1 rack.
Now how many Cell does it contain?Similar threads
