Current Generation Hardware Speculation with a Technical Spin [post GDC 2020] [XBSX, PS5]

[chris1515]

The XSX SoC has 76mb SRAM on board. More than enough in console space.

12 MB at least on the CPU 64 MB of SRAM for the GPU but there is many things out of cache using SRAM. I don't know if this is enough and the memory bandwidth of Xbox Series X is pretty high 560 GB/s interleaved with 336 GB/s. This is shared between the CPU and GPU but it is probably better than the rumored 384 GB/d of 6800 or 6700XT.

 

[QPlayer]

12 MB at least on the CPU 64 MB of SRAM for the GPU but there is many things out of cache using SRAM. I don't know if this is enough and the memory bandwidth of Xbox Series X is pretty high 560 GB/s interleaved with 336 GB/s. This is shared between the CPU and GPU but it is probably better than the rumored 384 GB/d of 6800 or 6700XT.

The Series X has tremendous memory bandwidth thanks to SFS memory management. We'll see how this will show in performance in the second and third waves of games.

 

[PSman1700]

The Series X has tremendous memory bandwidth thanks to SFS memory management. We'll see how this will show in performance in the second and third waves of games.

Yes because even 560GB/s seems kinda on the conservative side, they had to implement this SFS to counter that.

 

[3dilettante]

The SeriesX isn't using infinity cache for sure because they've shown the die's x-ray and there's a slide with the chip's total SRAM breakdown with no sign of any GPU LLC.
For the PS5 it's still unknown. Cerny did mention a "generous amount of SRAM" that the I/O complex would have access to, but the diagrams shown suggest it was for exclusive use of that block.

There's "generous" in a IO controller context and then there's extravagance with the capacities being thrown around in the rumors. Barring some kind of stacking or density miracle, the estimates of the PS5 SOC's size would need to include around 130mm2 for storage, and if the Series X die shot is a guide, the PS5 estimate seems in line with the usual contents in the SOC.
If there were that much storage, Sony could run 4 PS2 systems out of cache, although not enough to completely cache a PS3.

 

[pjbliverpool]

The Series X has tremendous memory bandwidth thanks to SFS memory management. We'll see how this will show in performance in the second and third waves of games.

All DX12U class devices can benefit from the memory bandwidth savings offered by Sampler Feedback. So the raw memory bandwidths should still be comparable, with the rumoured infinity cache, if it exists being the potential performance multiplier in the PC parts.

 

[iroboto]

There's "generous" in a IO controller context and then there's extravagance with the capacities being thrown around in the rumors. Barring some kind of stacking or density miracle, the estimates of the PS5 SOC's size would need to include around 130mm2 for storage, and if the Series X die shot is a guide, the PS5 estimate seems in line with the usual contents in the SOC.
If there were that much storage, Sony could run 4 PS2 systems out of cache, although not enough to completely cache a PS3.

since we're on topic, would infinity cache operate independently of L1 and L2 cache as in the same method of say esram in XBO as a separate sort of L3? Or does infinity cache just represent larger caches for L2 and L1?

 

[Jay]

I've never bought into PS5 infinity cache rumors, SOC size doesn't support it.

What I do think could be done on all RDNA2 devices or even just PC(with larger size) and PS5 is optimized cache where same structure as infinity cache but with normal size.
If the cache is shared between CU's then it will save on duplicated data, maximizing the cache size.
Main issue is supporting logic, and if all that works out a net benefit with normal cache size.

 

[BRiT]

If the cache is shared between CU's then it will save on duplicated data, maximizing the cache size.
Main issue is supporting logic, and if all that works out a net benefit with normal cache size.

I think that was part of RDNA 1, no?

 

[Jay]

I think that was part of RDNA 1, no?

Oh ok, so infinity cache is just lot larger cache then?

 

[Deleted member 13524]

There's "generous" in a IO controller context and then there's extravagance with the capacities being thrown around in the rumors.

What rumors are we talking about? I don't remember seeing any rumor about GPU LLC on the PS5. What capacities are mentioned in said rumors?

Barring some kind of stacking or density miracle, the estimates of the PS5 SOC's size would need to include around 130mm2 for storage, and if the Series X die shot is a guide, the PS5 estimate seems in line with the usual contents in the SOC.

Where are you taking the 130mm^2 number from? Are you also assuming the PS5 would use the same rumored 128MB as the 80 CU Navi 21?
If so, why would a 36 CU design have the same last level cache amount as a 80 CU one?

 

[3dilettante]

since we're on topic, would infinity cache operate independently of L1 and L2 cache as in the same method of say esram in XBO as a separate sort of L3? Or does infinity cache just represent larger caches for L2 and L1?

The rumors are not consistent on this. I think one rumor has it outside the L2.
Whether it's a massive cache is still unconfirmed from the evidence I've seen so far.
There are signs that there are changes being made, and it would seem like the upcoming RDNA discrete GPU would need something to compensate for a narrower than expected bus. However, whether there is a new level or if it's really the size some claim isn't clear. Some of the data points come from code that sometimes gives theoretical maximums for some of its constants, and one maximum in various driver sections is a maximum buffer size of 128MB. Just because code mentions that size doesn't mean the physical chip has it.
It's not certain a change in how some caches handle certain memory regions means there's a new cache, either.

 

[3dilettante]

What rumors are we talking about? I don't remember seeing any rumor about GPU LLC on the PS5. What capacities are mentioned in said rumors?

The rumors of a 128MB Infinity Cache for big Navi. There was speculation elsewhere that other RDNA2 GPUs would have it. I thought you were referencing those discussions.

Where are you taking the 130mm^2 number from? Are you also assuming the PS5 would use the same rumored 128MB as the 80 CU Navi 21?
If so, why would a 36 CU design have the same last level cache amount as a 80 CU one?

The nearest example to a large 7nm SRAM pool on this scale is AMD's Zen2 L3, which gives roughly 1 mm2 per MB.
A smaller GPU doesn't need to have the same capacity, if it's a cache, but I thought you were referencing speculation on that size in particular.

 

[QPlayer]

All DX12U class devices can benefit from the memory bandwidth savings offered by Sampler Feedback. So the raw memory bandwidths should still be comparable, with the rumoured infinity cache, if it exists being the potential performance multiplier in the PC parts.

SFS on the Series consoles is hardware-exclusive. SFS is approximately three times more efficient than normal SF on PCs. Effectively XSX requires a third as much bandwidth to move textures. This leaves plenty of extra bandwidth with special effects, raytracing, etc.

 

[Jay]

SFS on the Series consoles is hardware-exclusive. SFS is approximately three times more efficient than normal SF on PCs. Effectively XSX requires a third as much bandwidth to move textures. This leaves plenty of extra bandwidth with special effects, raytracing, etc.

Where did you get these comparative figures from?
Can't remember seeing that comparison before.

 

[BRiT]

Where did you get these comparative figures from?
Can't remember seeing that comparison before.

You've seen this all before, likely just can't remember it. The overall SFS efficiency was touted as 2.5x-3x I/O ratio and that included non texture data reads in the calculations. The slides from Hot Chips presentation is probably the more definitive place than interviews and tweets from Xbox Engineering (Spencer or Beard guy).

 

[Jay]

You've seen this all before, likely just can't remember it. The overall SFS efficiency was touted as 2.5x-3x I/O ratio and that included non texture data reads in the calculations. The slides from Hot Chips presentation is probably the more definitive place than interviews and tweets from Xbox Engineering (Spencer or Beard guy).

Was that compared to SF?
i.e. DX12U SF VS Xbox SFS (this makes a big difference)

 

[BRiT]

Was that compared to SF?
i.e. DX12U SF VS Xbox SFS

That I do not know. I only recall the 2.5-3 numbers being said, not the exact context. I'd need to rewatch the HotChips presentation section and reread the SFS DX12U docs.

 

[chris1515]

That I do not know. I only recall the 2.5-3 numbers being said, not the exact context. I'd need to rewatch the HotChips presentation section and reread the SFS DX12U docs.

This is the DRAM benefit it means velocity architecture s equivalent to have 2.5 times more RAM.

https://www.tomshardware.com/news/microsoft-xbox-series-x-architecture-deep-dive

 

[BRiT]

Or the inverse of ram capacity is being able to load things 2.5 times faster since you're only loading 1 unit instead of 2.5 units.

 

[pjbliverpool]

SFS on the Series consoles is hardware-exclusive. SFS is approximately three times more efficient than normal SF on PCs. Effectively XSX requires a third as much bandwidth to move textures. This leaves plenty of extra bandwidth with special effects, raytracing, etc.

No, Sampler Feedback and Sampler Feedback Streaming can be a multiplier for DRAM size and bandwidth vs not using Sampler Feedback at all. Sampler Feedback Streaming as used by the XSX is just a refinement of Sampler Feedback as used in all DX12U capable hardware to smooth over texture mip transitions in hardware when the required mip isn't transferred into video memory in time for the completed frame.