Anand has the details about r520,rv530,rv515

Tim said:
No there are no vanillas any more this generation and there are three versions of the the x1300LE. A 128bit memory version, a 64bit memory version and a HyperMemory version.
Well, guess we'll see who's right very soon ;)
 
Jawed said:
Those "relative performance" numbers are very interesting:

RV515 - 1
RV530 - 3
R520 - 5

I thought so too until I realized this is a marketing document and those numbers mean absolutely nothing. R520 is five times better than RV515 how? I'd rather take a 3DMark score than those figures.
 
Yeah - I'm dubious about the 5, too. 3 isn't believable either. I pointed them out to see what bites...

Jawed
 
wireframe said:
I thought so too until I realized this is a marketing document and those numbers mean absolutely nothing. R520 is five times better than RV515 how? I'd rather take a 3DMark score than those figures.

Well, the rv515 does 2000k+ in 3dmark (and thats assuming that the RV515 scores were legit), then that means the r520 will break the 10k mark!!!!

/me runs for cover..... :)
 
geo said:
Hexus has been rummaging in the dumpsters at ATI again, and claim to have the final pricing for X1xxx line (if the ketchup didn't obscure anything).

http://www.hexus.net/content/item.php?item=3566

A 256mb X1800XT? Personally, I wouldn't save $50 that way. Maybe $100 would give me pause, but not $50.
I agree 512MB is worth the extra $50 as it has already started showing significant gains.

http://www.amdzone.com/modules.php?...s&file=index&req=viewarticle&artid=182&page=2

(Me Likes the new Hexus website.)
 
Jawed said:
Those "relative performance" numbers are very interesting:

RV515 - 1
RV530 - 3
R520 - 5

Jawed

We don´t know how these relative performance numbers are derived, so the usefullness are limited, here are my thoughts anyway:

RV515 1/4=0.25
RV530 3/12=0.25
R520 5/16=0.31

So the R520 performas a little better per shader unit than the RV530 (the clock speed is suposed to be about equal for the RV530 and the R520), not suprising since the R520 is suposed to have twice the TMU and four times the ROPs. The RV530 still looks like the most interesting part from Ati this time around - I am looking forward to see how the performance/transistor for this part looks.

The RV515 is clocked lower so it not suprising that it performs lower per unit than the R520.
 
Dave Baumann said:
RV530 Shader processors = 12.

Has the penny dropped on 4-1-3-2 yet? (or at least, part of it?).
I'm still sticking to:
  • pipes per "array"
  • count of TMU arrays
  • count of shader arrays
  • count of ROP arrays
So 4 texture pipes, 3 quads of shader pipes, and 8 ROPs.

Although I don't think ROPs will be in arrays, strictly. Array "implies" SIMD.

Jawed
 
Dave Baumann said:
RV530 Shader processors = 12.

Has the penny dropped on 4-1-3-2 yet? (or at least, part of it?).

This will be a two page section of your R5xx architectural review section right? Titled something like "Look Here You Fools. . ."

Edit: Because I'll be one of the Fools reading it. I read your post upstream and went "Huh, Wavey just said that R520 has 20 shaders." Then I contemplated the frying pan and changed my mind.
 
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Jawed said:
Those "relative performance" numbers are very interesting:

RV515 - 1
RV530 - 3
R520 - 5

Jawed
That reminds me... sounds similar to the MS "Vista" power scheme discussed in the past... hmmm.
 
geo said:
This will be a two page section of your R5xx architectural review section right? Titled something like "Look Here You Fools. . ."

Edit: Because I'll be one of the Fools reading it. I read your post upstream and went "Huh, Wavey just said that R520 has 20 shaders." Then I contemplated the frying pan and changed my mind.
Acert's head explodes.

Really, so many theories on what those numbers mean. Dave better dedicate a full two pages to this after all these 30+ page R520 threads (heh, I started one even :cool: ).
 
Jawed said:
lthough I don't think ROPs will be in arrays, strictly. Array "implies" SIMD.
The only reason I say this is the memory interface.

If there's four 32-bit channels there's two arrangements of ROPs I can conceive of:
  • two quad-ROPs, each with a pair of memory controllers
  • four dual-ROPs, each with a memory controller
Both seem possible, but I thought I'd raise the question rather than just leaving it assumed.

In the end it comes down to how a render target is tiled in memory. I'm expecting a fairly big shake-up in tiling with R5xx.

Thinking about it some more, two quad-ROPs does actually marry up with the ring-bus diagram I drew a while back. In that diagram each quad-ROP has a pair of memory controllers. But I drew that before thinking about a new tiling scheme.

Jawed
 
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