AMD: Zen 2 (Ryzen/Threadripper 3000?, Epyc 8000?) Speculation, Rumours and Discussion

Discussion in 'PC Industry' started by ToTTenTranz, Oct 8, 2018.

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  1. xEx

    xEx
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    I was a little disappointed cuz there was no announcement rather than "its real and performs well" We will have to wait to see how well but it seems that for 2020 AMD and Intel will be fighting as equals. But We will see after that what will happen with Jim and Raya designs I cant imagine what someone like Jim would do with infinite resources and budged but I do think AMD approached splinting the CPU was better than Intels stacking.

    https://www.anandtech.com/show/1385...yzen2000?utm_source=twitter&utm_medium=social

    No APUs apparently too much latency(?) or maybe TDP? I was hopping to see an APU of Zen2 + Navi or maybe a 1CCXZen2+Navi on one die and HBM on the other... Anyways I just hope they lunch in April so I can get one. I pretty sure my F350 strix will get PCI4 support and if the rumors are true I can wait to have my 8core 5GHz CPU :D


    PD: So Adored was(at least half(?)) right, what a time to be alive.
     
  2. 3dilettante

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    The IO offered by EPYC isn't 4x a Summit Ridge die, so a combined uncore would likely skip IO interfaces that the socket wouldn't support and combine control blocks that some of the dies turn off if mounted in an MCM.
    EPYC seems like it might use half of the total amount of ports, whereas an IO die for one desktop CPU needs 1:1 match the socket featureset.

    Could be a delay in getting Navi ready for that kind of architecture, or issues with size or connectivity. The APU chiplet rumor that also had the chiplet be part of multiple discrete GPU products was one of the harder ones to reconcile.
    Where would the GDDR interface go for both APU and discrete? What's the power and manufacturing cost to splitting a high-bandwidth client like the GPU off from an on-die controller, or what's the area and die cost if the GPU has an inactive GDDR interface when mounted along with a CPU?

    Or somewhat less? I think he released a later video disavowing the IO die.
     
  3. xEx

    xEx
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    Its also possible that current MoBos wouldn't be ready for it and they need new specs and priories compatibility.

    I do think he got access to early info and targets so his sources were real.
     
  4. Rootax

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    I'm really interested in this. I believe by the end of the year I'll upgrade my 5820k@4.2ghz, So I'm looking at Zen2 based threadripper, or the next HEDT Intel cpus.. If Zen2 really improve single thread performances, a jump to AMD is not out of the question...
     
  5. fellix

    fellix Hey, You!
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  6. Gubbi

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    Run with one 4GB DIMM ?

    Cheers
     
  7. Lightman

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    Yes, and still around 12% faster in single thread than 2700X assuming clock detection works properly.

    I'm mildly impressed already!
     
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  8. xEx

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    I still have a R3 1200 since I bought it when I had no money and never felt the need to upgrade cuz this cheap thing is enough for general use but now I'm planing to buy an around 200 bucks zen 2, so im sure i will feel a huge difference. Im really excited about zen2 but the wait is so long...lets see how worth it will be.
     
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  9. 3dilettante

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    The cache latencies appear to be mostly in line with the Zen+ hierarchy, with the exception of the L3 latencies stretching at least twice as far with the purported new chip.
    The DRAM situation is sub-optimal given the choice in speed and single-channel setup, so I am curious to see whether final tuning and after-market tweaks can reduce what looks like a 15-20ns deficit in DRAM latency versus some Zen chips in that database.
     
  10. fehu

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    I have just no idea how this works.
    Can the AM4 memory lanes allow to switch between dual channel / dual slot and quad channel / single slot?

    In an interview on anandtech was asked how a dual channel can feed 32 threads, and the response was a generic "we have a surprise".
     
  11. 3dilettante

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    AM4 has the pins for two channels of DDR4. Slots that are assigned to a channel share them, so there's no way to separate them into additional channels.

    My impression from the QA with AMD was that it was more generic than promising a surprise, just that there would be more information in the future.
    There are changes like enhanced support for higher speeds, more efficient controllers, more intelligent prefetching, and improved hit rates in the caches.
    These can raise the bandwidth of the existing channels somewhat, use what bandwidth there is better, or get more amplification out of the caches.

    More exotic methods are enhanced cache management instructions or possibly some kind of compression, though for client workloads explicit code for wrangling caches is unlikely to be used and compression is more of a server-level feature that may get some inconsistent capacity/bandwidth gains at a complexity and latency cost.
     
  12. Davros

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    DDR4 3200:25.6 GB/s
    PCI-e 5.0 16x: 63.0 GB/s

    Would it make sense to access ram via PCi-e ?
     
  13. Malo

    Malo Yak Mechanicum
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    Isn't that like putting an F1 car on the roof of a Ford Mustang?
     
  14. 3dilettante

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    EPYC's xGMI links send coherent requests over PCIe links.
    With the current fabric architecture, there would still need to be a CPU on the other end of the PCIe link, or at least memory controller. PCIe without xGMI and the associated hardware on the other end would not be coherently tracked, and would be much less useful than DDR4.

    When comparing DRAM, GMI, and xGMI links, the last one tends to be somewhat inferior in bandwidth due to additional error correction. Area-wise, PCIe appears to be worse than DDR4 on the Ryzen die shot.
    Power-wise, I'm not sure, but since PCIe itself is not designed to interface with multiple DRAM chips on a DIMM, a link would then need to incur the power and area cost of the DDR controller and PHY anyway.

    There are memory types that have serialized interfaces, though this requires more specialization than a generic expansion bus needs, and their physical and electrical standards don't need to be engineered for the slots and trace lengths expansion boards need.

    For AMD, it seems likely PCIe 5.0 is reserved for the next socket, and that brings in DDR5 at the same time.
     
  15. Davros

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    I forgot the limiting factor is the ram not the bus
     
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  16. xEx

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    Haven't found a text version yet. the vid starts right with specs on screen.

     
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  17. no-X

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    Those specs are identical to the (6 months old) AdoredTV table (e. g. here). It seems to be 3rd eshop, which tried to grab attention by inserting them to the product list. It's not easy to believe that Ryzen 3000 specs were finalized >7 months before launch and anything haven't changed since the end of November.
     
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  18. Rootax

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    The specs were finalized but maybe not "met" by production ? Or some bios / motherboard/ chipset problem ? I prefer a delay rather than the mess that was Zen launch.
     
  19. Alexko

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  20. ToTTenTranz

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    So Ryzen 9 effectively replaces the lower-end Threadripper at a fraction of the production cost for AMD. End users lose a bit of memory bandwidth (though they can probably use 4266MT/s DDR4 to compensate somehow), and they go from 64 PCIe 3.0 lanes to 24 PCIe 4.0 lanes effectively getting 75% of the bandwidth.
    I wonder if higher-end motherboards will offer MUX controllers that convert a 16x PCIe 3.0 bus into 8x PCIe 4.0.
     
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