AMD: Zen 2 (Ryzen/Threadripper 3000?, Epyc 8000?) Speculation, Rumours and Discussion

Discussion in 'PC Industry' started by ToTTenTranz, Oct 8, 2018.

  1. msia2k75

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    #141 msia2k75, Dec 15, 2018
    Last edited: Dec 15, 2018
  2. ToTTenTranz

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    Considering it's still a 14/12nm chip, the most important thing about Picasso is if it supports LPDDR4.
     
  3. tunafish

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    Desktop Ryzen 3000 CPUs will also use the same chiplets as EPYC. Just showed on stream.
     
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  4. ToTTenTranz

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    https://www.anandtech.com/show/13829/amd-ryzen-3rd-generation-zen-2-pcie-4-eight-core

    [​IMG]

    Same 8-core, 80mm^2 chiplet as Rome, and a new 123mm^2 I/O die.
    There's a clear space (almost with a big X marks the spot) that would/will receive a second CPU chiplet in higher end models. We might see 16 cores with AM4, though I wonder if a dual-channel memory bandwidth will ever be enough for that kind of compute power.

    The IO is made on GF 14nm again, since it's around a quarter of the size of Rome's huge IO die. It's still a very large die just for IO, so the chances of it having some kind of cache (L3? L4?) have increased IMO.


    Anandtech also mentions that dual-sourcing should make lower priced chips harder, so we shouldn't expect APUs to use these chiplets. Maybe they're going with the 200mm^2 form factor for the APUs.
     
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  5. shiznit

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    My guess is no cache on the IO die, the IF link can't handle that kind of throughput, it's sized for RAM/PCI-E interface width and low power. The more efficient approach would be to double the L3 on the chiplet where you have the bandwidth and low latency, in addition to 7nm SRAM scaling and reduction of traffic through the IO die.

    Area is another issue. If you look at the Zen1 die shot, the CCXs are ~1/2 of the area so it's not surprising the new IO die is also ~1/2. There's no room in 120mm for the uncore, an additional IF interface for second chiplet, and a cache large enough to make a difference.
     
    #145 shiznit, Jan 9, 2019
    Last edited: Jan 9, 2019
  6. Malo

    Malo YakTribe.games
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    I wonder if cooling would be affected in any way with uneven distribution to heat pipes/fins? Probably negligible depending on the cooler design.
     
  7. 3dilettante

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    I hope we get more details on the memory latency of the setup. AMD's choice of Cinebench may not be as representative of the workloads that saw benefits from tighter timings in prior Ryzen products.
    I wonder in this case of asymmetric layout if it's solder or TIM under the heatspreader.
     
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  8. Psycho

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    Any good reason to place the dies like that except for the mentioned 1+2 speculation? (which could also explain the relatively large size of the io die).
    If it was for heat distribution or easier edge-edge connections a regular diagonal layout would have been more obvious.
     
  9. fellix

    fellix Hey, You!
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    Considering the constrained package area, I don't think AMD had much of a choice for different layouts.
     
  10. milk

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    How about centralized?
     
  11. shiznit

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    Bingo. You can see the traces for the second chiplet from this angle:

    [​IMG]
     
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  12. tunafish

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  13. hoom

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    Interesting.
    Not directly a 1/4 IO chip :-( but looks like this one can at least be re-used for the 16 core version :smile2:
     
  14. Arzachel

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    It's the same amount of bandwidth per core as 64c Rome ;)
     
  15. ToTTenTranz

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    16 core Ryzen 3000 (or at least dual chiplet for >8 cores) confirmed by Lisa Su.




    You're right, 64c Rome is 8 channels, so 1 channel per 8 cores.
    And a consumer Ryzen would probably get substantially higher bandwidth per-core because they can be paired with DDR4 >3200MT/s memory, whereas Rome is limited to 2666 MT/s.

    My concern would be the fact that 32c Threadripper 2990WX seemed to be starving for bandwidth in many tests, but it seems that was the fault of a windows bug all the time.
     
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  16. Theeoo

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    Fits with AMD's M.O. of the past 7-8 years i.e. packing in more cores.
     
  17. 3dilettante

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    For EPYC, there are workloads where the bandwidth is a constraint. AMD made some statements about doing more to increase bandwidth over the first generation, and with current products there are different SKUs that emphasize cores, clocks, or memory over other factors. A customer with a bandwidth-limited workload may opt for one of the lower-count variants in order to reap cost and power savings, or possibly get some better single-threaded performance.
    A high occupancy VM host might opt for having more instances with the understanding that their bandwidth requirements will be modest.

    The consumer line may be a little constrained in order to avoid complicating the analysis for consumers, although there may be some applications that would have benefited from a product with a similarly targeted mix.
     
  18. fellix

    fellix Hey, You!
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  19. ToTTenTranz

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    https://www.digitimes.com/news/a20190111PD207.html

    TSMC does the packaging for Rome, whereas SPIL and TFME do the packaging for Ryzen 3000 and Vega VII.
     
  20. tunafish

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