AMD: Zen 2 (Ryzen/Threadripper 3000?, Epyc 8000?) Speculation, Rumours and Discussion

Wasn't the reddit leak hinted at that?


EDIT:

No it's different. Though the reddit leak was concerning desktop APU...

 

Desktop Ryzen 3000 CPUs will also use the same chiplets as EPYC. Just showed on stream.

 

My guess is no cache on the IO die, the IF link can't handle that kind of throughput, it's sized for RAM/PCI-E interface width and low power. The more efficient approach would be to double the L3 on the chiplet where you have the bandwidth and low latency, in addition to 7nm SRAM scaling and reduction of traffic through the IO die.

Area is another issue. If you look at the Zen1 die shot, the CCXs are ~1/2 of the area so it's not surprising the new IO die is also ~1/2. There's no room in 120mm for the uncore, an additional IF interface for second chiplet, and a cache large enough to make a difference.

 

I wonder if cooling would be affected in any way with uneven distribution to heat pipes/fins? Probably negligible depending on the cooler design.

 

I hope we get more details on the memory latency of the setup. AMD's choice of Cinebench may not be as representative of the workloads that saw benefits from tighter timings in prior Ryzen products.
I wonder in this case of asymmetric layout if it's solder or TIM under the heatspreader.

 

Any good reason to place the dies like that except for the mentioned 1+2 speculation? (which could also explain the relatively large size of the io die).
If it was for heat distribution or easier edge-edge connections a regular diagonal layout would have been more obvious.

 

Considering the constrained package area, I don't think AMD had much of a choice for different layouts.

 

How about centralized?

 

Bingo. You can see the traces for the second chiplet from this angle:

 

And just to confirm the obvious: Su mentioned to press that they intend to use the extra space.

 

Interesting.
Not directly a 1/4 IO chip but looks like this one can at least be re-used for the 16 core version

 

It's the same amount of bandwidth per core as 64c Rome

 

Fits with AMD's M.O. of the past 7-8 years i.e. packing in more cores.

 

For EPYC, there are workloads where the bandwidth is a constraint. AMD made some statements about doing more to increase bandwidth over the first generation, and with current products there are different SKUs that emphasize cores, clocks, or memory over other factors. A customer with a bandwidth-limited workload may opt for one of the lower-count variants in order to reap cost and power savings, or possibly get some better single-threaded performance.
A high occupancy VM host might opt for having more instances with the understanding that their bandwidth requirements will be modest.

The consumer line may be a little constrained in order to avoid complicating the analysis for consumers, although there may be some applications that would have benefited from a product with a similarly targeted mix.

 

Isn't CoWoS an interposer tech? Maybe that's for Milan, not Rome.