The GPU xGMI links are apparently running at 25 Gbps, going from the following video (after 21:00). found via reddit: Possibly, given the introduction of PCIe 4.0, there is something like the Synopsis multi-mode PHY used by Zen for its PCIe/xGMI purposes. The following, for example might be able to support PCIe 4.0 and a 25 Gbps connection as well. https://www.synopsys.com/dw/ipdir.php?ds=dwc_multi_protocol_25g_phy Another point further in the video is that the GPUs can be connected in a ring with comparatively low latency for a GPU, and that it's all encrypted. I'm not sure if that is carrying over from the MI60's implementing memory encryption, or if the links themselves can be encrypted. The latter point is something I'm curious about relative to EPYC and its encryption. The memory controllers decrypt memory as it is read in, and the isolation of unencrypted data in the caches is enforced by ASID--where a requester not from the same space misses in the cache goes to memory for decryption (or loading bad data?). However, that understandable way of handling things makes me curious when the data potentially moves off-chip, like in an MCM or over the xGMI links in a 2-socket system. Is the presumption that it's too difficult to intercept? Is a workaround like allocating a VM only to one chip so there's no transfer out possible? Does it become more of a question in Rome, where if data decrypts at the controller there is no avoiding an off-chip transfer? Could this mean there's been a change concerning what paths are encrypted/decrypted?