AMD: Southern Islands (7*** series) Speculation/ Rumour Thread

Totally fake. There is no reason to do a major shift to XDR2 when theres plenty of headroom left in GDDR5.

What "plenty of headroom" do you mean?

Making memory wider is expensive. And ATI/AMD does not seem to like non-power-of-2 memory bus widths. And there is 7 GHz(data rate) GDDR5 available, but that's not much more than the 5.5 GHz(data rate) 6970 currently has.
 
XDR2 will be really nice, but it's too good and way too expensive to be true. On the other hand, the micro-threading feature in XDR2 can really help a lot to speed up a wide range of GPGPU code.
Meh, it's just a dream!
 
What "plenty of headroom" do you mean?

Making memory wider is expensive. And ATI/AMD does not seem to like non-power-of-2 memory bus widths. And there is 7 GHz(data rate) GDDR5 available, but that's not much more than the 5.5 GHz(data rate) 6970 currently has.

Theres ~28% headroom without even changing the memory controller, and they could easily up the bus to 384 bit and have nearly 100% headroom, if they needed it. Thats probably enough for two generations/years.
 
- HD 7990 New Zealand GCN
- HD 7970 Tahiti XT GCN 1000MHz 32CUs 2048ALUs 128TMUs 64ROPs 256bit XDR2 8.0Gbps 256GB/s 2GB 190W HP
- HD 7950 Tahiti Pro GCN 900MHz 30CUs 1920ALUs 120TMUs 64ROPs 256bit XDR2 7.2Gbps 230GB/s 2GB 150W HP
- HD 7870 Thames XT VLIW4 950MHz 24SIMDs 1536ALUs 96TMUs 32ROPs 256bit GDDR5 5.8Gbps 186GB/s 2GB 120W HPL
- HD 7850 Thames Pro VLIW4 850MHz 22SIMDs 1408ALUs 88TMUs 32ROPs 256bit GDDR5 5.2Gbps 166GB/s 2GB 90W HPL
- HD 7670 Lombok XT VLIW4 900MHz 12SIMDs 768ALUs 48TMUs 16ROPs 128bit GDDR5 5.0Gbps 80GB/s 1GB 60W HPL
- HD 7570 Lombok Pro VLIW4 750MHz 12SIMDs 768ALUs 48TMUs 16ROPs 128bit GDDR5 4.0Gbps 64GB/s 1GB 50W HPL

XDR 2 wooot

source

Already posted + fake
And Thames isn't even desktop chip, it's laptop.
 
Obviously the XDR2 rumors (which last time I checked no one had signed on to create even though the spec has been around FOR YEARS because everyone hates Rambus) and this conversation are dancing around a question that doesn't have an easy answer. That is, if the mid-range part is 256-bit with ~5ghz, how does a higher-end part approx double that?

1. 256-bit XDR2 (erm...)
2. 384-bit @ ~7gbps
3. 512-bit @ 5gbps


While I agree 384-bit makes both the most sense considering the up-to-now AMD strategy of ramping voltage/clockspeeds in place of physical logic, it seems the least likely considering they have no precedence in using odd buses. I also think it makes sense because of the 1.5/3GB configuration options considering the most-used resolution and what it requires, which could help cut costs, not-to-mention 6/12x6-7gbps @ 1.5v on paper sounds better than 8/16x4-5gbps @ 1.35v. OTOH, voltage on 28nm HP is 1.05v, and HLP (if that rumor is true) 1v flat, down from the 1.2v of virtually every other process they've used up to this point (not counting the 1.3v spec they helped create and used on 55nm), close/identical to the nVIDIA standard 1v operating voltage across all those same processes (and they'll probably use again.) In other words, they may not have that option this go-round, and may be forced to use more logic and have larger dies than we've seen since RV670 to remain competitive. Therefore, a larger bus may make sense.

I imagine we're all on the same page with what nVIDIA's likely to do with Kepler and the GF104/114 refresh, why wouldn't AMD go this route? Just because of R600?

While increasing the number of memory controllers is expensive, so is increasing their speed. Recalling Anand's Barts review, AMD mentioned that the Cypress controller was around twice the size of Redwood (article expounds they mean per controller...obviously one is 128-bit, the other 256-bit) which sounds like a dramatic decrease in returns for a 15% gain. One could imagine then what it would take to run a controller at around 7Gbps. In essence, that statement is an admittance that more controllers running at a lower speed (ala Barts) IS a good option.

Now, granted, 512-bit would mean a large chip...and 28nm is immature. I think it's the consensus though the largest chip will come later, sometime in 2012, and what we'll get for 2011 is a Cypress replacement. Hence, it's at least plausible.

One could go on and on and run circles around each option. That opinion could be tainted on wither you believe the mid-range will be a 192-bit chip as DH originally posted and Charlie omitted regarding mobile variations, or rather still a 256-bit chip (that DH had pegged further out into 2012, and Charlie's mobile chart included). At this point, considering 192-bit could be seen as a step backwards from Barts, I'm inclined to believe the mid-range is 256-bit.

I'm not making a definitive argument for 512-bit, but it makes just as much sense as 384-bit when considering the known variables which I'm aware...and a hell of a lot more than XDR2 afaik. No one seems to mention it though...so I thought I would :)
 
Actually my guess is on die cache rather than increasing RAM bandwidth. Hasn't there been a trend towards increasing bandwidth efficiency faster than actual delivered bandwidth?
 
OTOH, voltage on 28nm HP is 1.05v, and HLP (if that rumor is true) 1v flat, down from the 1.2v of virtually every other process they've used up to this point (not counting the 1.3v spec they helped create and used on 55nm), close/identical to the nVIDIA standard 1v operating voltage across all those same processes (and they'll probably use again.)
The nominal voltage of the 28HP process is just 0.85V (40G has 0.9V but AMD as well as nv used to "overdrive", which is said to be problematic on TSMCs 28nm gate last process).
 
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