AMD: Southern Islands (7*** series) Speculation/ Rumour Thread
- Thread starter UniversalTruth
- Start date
Besides this being regurgitated info of the stuff that's been flying around the net for months?
nope
Definitely.
All 'specs' that tout Thames as mid-range desktop are fake by default, because with 99.99% certainty Thames is just the mobile version of Lombok.
Ninjaprime
Regular
Totally fake. There is no reason to do a major shift to XDR2 when theres plenty of headroom left in GDDR5.
I am more than happy to be wrong in this case :smile:
What "plenty of headroom" do you mean?
Making memory wider is expensive. And ATI/AMD does not seem to like non-power-of-2 memory bus widths. And there is 7 GHz(data rate) GDDR5 available, but that's not much more than the 5.5 GHz(data rate) 6970 currently has.
Ninjaprime
Regular
Theres ~28% headroom without even changing the memory controller, and they could easily up the bus to 384 bit and have nearly 100% headroom, if they needed it. Thats probably enough for two generations/years.
Man from Atlantis
Veteran
opps my bad i just get up and saw the rumours wanted to share.. next time i'll be more careful
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Obviously the XDR2 rumors (which last time I checked no one had signed on to create even though the spec has been around FOR YEARS because everyone hates Rambus) and this conversation are dancing around a question that doesn't have an easy answer. That is, if the mid-range part is 256-bit with ~5ghz, how does a higher-end part approx double that?
1. 256-bit XDR2 (erm...)
2. 384-bit @ ~7gbps
3. 512-bit @ 5gbps
While I agree 384-bit makes both the most sense considering the up-to-now AMD strategy of ramping voltage/clockspeeds in place of physical logic, it seems the least likely considering they have no precedence in using odd buses. I also think it makes sense because of the 1.5/3GB configuration options considering the most-used resolution and what it requires, which could help cut costs, not-to-mention 6/12x6-7gbps @ 1.5v on paper sounds better than 8/16x4-5gbps @ 1.35v. OTOH, voltage on 28nm HP is 1.05v, and HLP (if that rumor is true) 1v flat, down from the 1.2v of virtually every other process they've used up to this point (not counting the 1.3v spec they helped create and used on 55nm), close/identical to the nVIDIA standard 1v operating voltage across all those same processes (and they'll probably use again.) In other words, they may not have that option this go-round, and may be forced to use more logic and have larger dies than we've seen since RV670 to remain competitive. Therefore, a larger bus may make sense.
I imagine we're all on the same page with what nVIDIA's likely to do with Kepler and the GF104/114 refresh, why wouldn't AMD go this route? Just because of R600?
While increasing the number of memory controllers is expensive, so is increasing their speed. Recalling Anand's Barts review, AMD mentioned that the Cypress controller was around twice the size of Redwood (article expounds they mean per controller...obviously one is 128-bit, the other 256-bit) which sounds like a dramatic decrease in returns for a 15% gain. One could imagine then what it would take to run a controller at around 7Gbps. In essence, that statement is an admittance that more controllers running at a lower speed (ala Barts) IS a good option.
Now, granted, 512-bit would mean a large chip...and 28nm is immature. I think it's the consensus though the largest chip will come later, sometime in 2012, and what we'll get for 2011 is a Cypress replacement. Hence, it's at least plausible.
One could go on and on and run circles around each option. That opinion could be tainted on wither you believe the mid-range will be a 192-bit chip as DH originally posted and Charlie omitted regarding mobile variations, or rather still a 256-bit chip (that DH had pegged further out into 2012, and Charlie's mobile chart included). At this point, considering 192-bit could be seen as a step backwards from Barts, I'm inclined to believe the mid-range is 256-bit.
I'm not making a definitive argument for 512-bit, but it makes just as much sense as 384-bit when considering the known variables which I'm aware...and a hell of a lot more than XDR2 afaik. No one seems to mention it though...so I thought I would
1. 256-bit XDR2 (erm...)
2. 384-bit @ ~7gbps
3. 512-bit @ 5gbps
While I agree 384-bit makes both the most sense considering the up-to-now AMD strategy of ramping voltage/clockspeeds in place of physical logic, it seems the least likely considering they have no precedence in using odd buses. I also think it makes sense because of the 1.5/3GB configuration options considering the most-used resolution and what it requires, which could help cut costs, not-to-mention 6/12x6-7gbps @ 1.5v on paper sounds better than 8/16x4-5gbps @ 1.35v. OTOH, voltage on 28nm HP is 1.05v, and HLP (if that rumor is true) 1v flat, down from the 1.2v of virtually every other process they've used up to this point (not counting the 1.3v spec they helped create and used on 55nm), close/identical to the nVIDIA standard 1v operating voltage across all those same processes (and they'll probably use again.) In other words, they may not have that option this go-round, and may be forced to use more logic and have larger dies than we've seen since RV670 to remain competitive. Therefore, a larger bus may make sense.
I imagine we're all on the same page with what nVIDIA's likely to do with Kepler and the GF104/114 refresh, why wouldn't AMD go this route? Just because of R600?
While increasing the number of memory controllers is expensive, so is increasing their speed. Recalling Anand's Barts review, AMD mentioned that the Cypress controller was around twice the size of Redwood (article expounds they mean per controller...obviously one is 128-bit, the other 256-bit) which sounds like a dramatic decrease in returns for a 15% gain. One could imagine then what it would take to run a controller at around 7Gbps. In essence, that statement is an admittance that more controllers running at a lower speed (ala Barts) IS a good option.
Now, granted, 512-bit would mean a large chip...and 28nm is immature. I think it's the consensus though the largest chip will come later, sometime in 2012, and what we'll get for 2011 is a Cypress replacement. Hence, it's at least plausible.
One could go on and on and run circles around each option. That opinion could be tainted on wither you believe the mid-range will be a 192-bit chip as DH originally posted and Charlie omitted regarding mobile variations, or rather still a 256-bit chip (that DH had pegged further out into 2012, and Charlie's mobile chart included). At this point, considering 192-bit could be seen as a step backwards from Barts, I'm inclined to believe the mid-range is 256-bit.
I'm not making a definitive argument for 512-bit, but it makes just as much sense as 384-bit when considering the known variables which I'm aware...and a hell of a lot more than XDR2 afaik. No one seems to mention it though...so I thought I would
Jawed
Legend
Seems like it to me.
The nominal voltage of the 28HP process is just 0.85V (40G has 0.9V but AMD as well as nv used to "overdrive", which is said to be problematic on TSMCs 28nm gate last process).
At least some of the cards from HD7 series this year
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