You can mix different transistors on the same node, so 40G + 40LP for example, but not something like 40 + 28. The materials + lithography are too tightly coupled.
AFAIK, some mixed signal ICs mix processes as analog circuits scale poorly.
You can mix different transistors on the same node, so 40G + 40LP for example, but not something like 40 + 28. The materials + lithography are too tightly coupled.
+1.It's garbage. But atleast it delivers it's promise of wildness.
You probably meant 16 ROPs there...Being VLIW4, Lombock could be.. half a Cayman? That would be 768 VLIW4 cores, 48 TMUs and 15 ROPs.
I think that's possible though the chip might be slower...Notice how there's no info on lower end than Lombock, suggesting that graphics cards on that performance level will be replaced by APUs.
I mentioned in the past that I believe Trinity is not going to exceed 8 simds (512 shader units). So if AMD is going to do a similar discrete chip it could be the same.Could Trinity carry a Lombock inside? That would more than double Llano in processing power.
Imagine a Tryinity + crossfired Lombock in a laptop.
You can mix different transistors on the same node, so 40G + 40LP for example, but not something like 40 + 28. The materials + lithography are too tightly coupled.
Has anyone seen this?
If:
Tahiti has 3200 GCN cores 128 TMUs, 48 TMUs,
then
Thames should be 1600 GCN cores, 64 TMUs and 24 ROPs.
Meaning Southern Islands could be a 2x jump from Evergreen in the mid-high to ultra-high end.
Being VLIW4, Lombock could be.. half a Cayman? That would be 768 VLIW4 cores, 48 TMUs and 15 ROPs.
Notice how there's no info on lower end than Lombock, suggesting that graphics cards on that performance level will be replaced by APUs.
Could Trinity carry a Lombock inside? That would more than double Llano in processing power.
Imagine a Tryinity + crossfired Lombock in a laptop.
With the important caveat that, for the mixed case, both G and LP characteristics will be worse than the pure equivalent.Rys said:You can mix different transistors on the same node, so 40G + 40LP for example, but not something like 40 + 28. The materials + lithography are too tightly coupled.
The source of those spec is a joke post from NOVEMBER 2010 made at semiaccurate forums. They first appeared one day before GTX590 launch in march, now a second time. Will we see a third? Oh, and if the autor knew back then we would have a new architecture, I am sure he would generated something more apropiate.Those fake-slide-makers should be ashamed for making so low-qualiy fakes; they should even TRY to understand the architecture so that they could make more believable fake slides.
The numbers don't quite fit the previous VLIW-5 or VLIW-4 architectures neither. But well if it never wasn't meant seriously it doesn't really matter .Oh, and if the autor knew back then we would have a new architecture, I am sure he would generated something more apropiate.
With the important caveat that, for the mixed case, both G and LP characteristics will be worse than the pure equivalent.
And it's quite a more expensive too.
True about the level shifters. I could have sworn I saw a TSMC slide at some point about some (minor) trade-offs, but I never really checked the libraries, so I could be wrong.That hasn't been my experience.
I've worked on chips where both G and LP cells were used. Partitions using G cells don't use LP cells and vice versa, and G partitions operate on different power domain than LP partition. You make sure signals crossing over from G<->LP have proper level shifters etc.
Other than these restrictions I don't know of any serious issues or drawbacks.
There's a fairly high chance of that on Fermi designs, yep.The former was what I had in mind. Is that possibly what Nvidia has done with GF11x?
40LPG makes no sense here IMO. Remember that dynamic power per MHz is *lower* on 40G than 40LP (although performance is higher so power per transistor is still higher on 40G). It's low power in terms of leakage, not necessarily overall power. They need to invest more in power gating, not low leakage transistors. The same is true for AMD obviously, but that's not a very good reason to keep this off-topic conversation goingThere's a fairly high chance of that on Fermi designs, yep.
40LPG makes no sense here IMO. Remember that dynamic power per MHz is *lower* on 40G than 40LP (although performance is higher so power per transistor is still higher on 40G). It's low power in terms of leakage, not necessarily overall power. They need to invest more in power gating, not low leakage transistors. The same is true for AMD obviously, but that's not a very good reason to keep this off-topic conversation going
The source of those specs was a post by the user 265586888 at semiaccurate forums. Actually, he was just taking a stab at all those speculations floating around. It is pure irony that it was picked up as rumor.Those fake-slide-makers should be ashamed for making so low-qualiy fakes; they should even TRY to understand the architecture so that they could make more believable fake slides.
Nothing off topic about this subject.Missed the "off topic" memo.
40G and 40LP have different voltages. Is the same true for different 28nm variants? Or do they all use the same vdd?