AMD: Southern Islands (7*** series) Speculation/ Rumour Thread

The rumour mongers should launch the rumour that AMD is working with Elpida to create buried TSV DRAM stacks for use as fast storage ... I'd like to see it happen

With Elpida sampling TSV DDR3 the technology should be almost ready (the buried DRAM layout is "just" a stack of TSV DRAM chips flipchip bonded to the bottom of the GPU chip, with a corresponding hollow in the carrier substrate ... obviously you would want a higher density of TSVs than with DDR3 though).

 

Even Charlie is not claiming AMD is going to use the LP process (he suggests HPL). TSMC offers four 28nm processes: LP, HPL, HPM, and HP (with nominal Vcc 1.05, 1.0, 0.9, and 0.85V respectively). While all HPx are using HKMG, HPL misses the SiGe strain.
Xilinx is using HPL for it's FPGAs and has quite a few pdfs touting its advantages over HP for reducing leakage and getting the same or higher performance in (static) power constrained scenarios. As leakage/static amounts to maybe 40% of the total power consumption of current GPUs, it appears quite sure GPU manufactures will look into the reasoning of Xilinx.

 

Besides, if AMD can indeed pull off a 6-month lead over NVIDIA in 28nm, as Charlie expects, they could probably get away with relatively low clocks, something like 700~750MHz, thereby minimizing the influence of dynamic power, and perhaps getting back to a 150~200W level for high-end cards. Naturally, that would also make dual-chip cards easier.

They could always migrate to HP 6 months later, à la RV790.

 

At lower clocks, leakage is lower, making dynamic power the dominant one. Besides, the HPL process would have been optimized for low leakage anyway. At any rate, I would not expect >4 months lead for AMD this time.

I don't think that is an investment they will be willing to make.

 

I believe leakage is a function of voltage², not clocks. Of course, higher clocks do require higher voltages.

 

Well, right there you have the relation between leakage and clocks.

 

Well yes, but dynamic power is a function of voltage² × frequency, which essentially boils down to frequency³ as you usually have to increase voltage linearly as you increase frequency.

So as frequency rises (resp. diminishes) the percentage of power represented by leakage diminishes (resp. increases).

 

IIRC, a far bigger dependency is on threshold voltage and device parameters.

 

BTW - has it been mentioned here that AMD has working 28-nm-silicon in house for their next generation 28nm products?

http://seekingalpha.com/article/281...sses-q2-2011-results-earnings-call-transcript

 

By now, I'd be very worried if they didn't!

 

IMHO that depends if we're talking about late Q3 or late Q4 for productization.

 

Even for late Q4, they'd better have silicon right now.

 

As I mentioned Xilinx already, this is a graph of them comparing leakage with LP, HPL and HP when scaling a design to different performance points:



They label the region at the top end as suitable for GPUs, but considering the power constraints we have already today and the expected doubling of transistors with the next generation, they may also be better off with HPL or at least they may come quite close to the intersection point.
In other words, the power constraints for a high end GPU with probably 5 to 6 billion transistors, may render the region where the HP process offers higher performance/W unattractive. After all, they have already up to 100W consumption due to leakage (in 40nm). Considering that HPL is probably cheaper and has higher yields (no SiGe), one may be able to live with a slightly larger die putting in a few more units to partially compensate for the loss on clockspeed. And the idle consumption will be much lower (Xilinx is also claiming a quite limited voltage scalability of the HP process, one can't go far down).

 

100W consumption due to leakage? I have no idea what the actual figure could be but 100 W is like one-third the power consumption of Fermi!

Well AMD stopped using the HP process anyway when they abandoned the large die strategy for the sweet spot strategy so it wouldnt be surprising that they dont go for HP this time around as well.

What are the advantages(if any) of 28 LP over 28 HPL though? From the graph it appears that HPL has much lower leakage for the same performance.

 

Did they? I always thought they used 40G, which is the 40nm equivalent of 28HP.

 

Well maybe im mistaken then, i thought there was another high performance process above 40G. IIRC they used the HP process from 90nm to 65nm, and when they launched RV670 and RV770 at 55nm, i remember reading that they would start using power optimised processes rather than high performance processes in line with their sweet spot strategy.

 

Price? (SiON vs. HKMG)

 

Sorry if this has been asked before, but how do you think these are gonna perform mining bitcoins?

Is there going to be a performance increase, or maybe a decrease because they are using less more complex shaders?

Thankss

 

Assuming the shaders will still do the 32-bit integer right rotate op in one cycle (Fermi emulates that in three cycles) it should be a matter of what peak GFLOPs the cards will provide.

 

Yes, it is. Just run a Fermi at nominal voltage in idle and see for yourself. There is a reason AMD/nvidia reduces the voltages in idle aggressively.

It is cheaper and you can probably get a bit denser layout. If you don"t care about performance (i.e. it is high enough anyway), LP is the way to go.