AMD RyZen CPU Architecture for 2017

[Clukos]

Things take time on the server side that's for sure, at least the future for AMD looks very bright in terms of competition (and something needed in the industry). 7nm GloFo is shooting for 5GHz operations for server hardware, if they manage to hit that, the performance will be very impressive indeed.

 

[3dilettante]

The slide:


One have to question after all of wcc comments if ur gonna quote them why quote the most general and probably repeated on well known sites quote?

One difference is that this is the one specific sentence that mentions Naples and the "four years" phrase positioned in a way that it can be mangled to say what it does in the slide. The source PCWorld article title, for example, just says Zen.
Intel's slide couldn't use that title to target AMD's server chip in particular.

It's not really about Wccftech's. What little is left of its title has stripped out any analysis or thought the site may have had, and most of its factual value as well. It might not be fair to say it's a quote, and I'm not sure what reasons Intel had for taking that route there would that aren't very unflattering.

If someone had one of those sets of magnetic poetry words on their fridge that happened to have AMD, Naples, four, and years somewhere in the mass--Intel might have quoted that too.

 

[Clukos]

Epyc will be socket compatible with the next generation. @3:50

@7:31

 

[xEx]

One difference is that this is the one specific sentence that mentions Naples and the "four years" phrase positioned in a way that it can be mangled to say what it does in the slide. The source PCWorld article title, for example, just says Zen.
Intel's slide couldn't use that title to target AMD's server chip in particular.

It's not really about Wccftech's. What little is left of its title has stripped out any analysis or thought the site may have had, and most of its factual value as well. It might not be fair to say it's a quote, and I'm not sure what reasons Intel had for taking that route there would that aren't very unflattering.

If someone had one of those sets of magnetic poetry words on their fridge that happened to have AMD, Naples, four, and years somewhere in the mass--Intel might have quoted that too.

Wel...by definition its a quote. there is not limit in how large a quote has to be to be a quote. they showed something that Wcc said in literal way so its a quote.

And If intel can quote them, so can anyone in the net as well.

 

[3dilettante]

Were the Anandtech memory latency numbers done for one socket?

Zen's architecture overall does reward a specific level of locality of core activity and memory communication, and Anandtech's preliminary numbers are admitted to be from time-limited testing. Intel's contention that there are going to be inconsistencies in performance whenever a workload doesn't cater to Zen's specific structure and avoids some areas where it is mediocre may be fair. Even workloads that mostly fit in a CCX can suffer from a death by a thousand cuts, and Anandtech does postulate that Zen's higher gain with SMT comes down to it having more performance lost thanks to the poor latency of the subsystem.

AVX is proving to be something of a bear for Intel and AMD. There were cracks in Intel's power management and clock consistency that seem to have gotten worse, which shows that having rather extreme capability isn't free. That, and the sparseness of the adoption of the most advanced extensions may give Naples something of a buffer versus the competition, at least for now and outside of specific fields that AVX-512 was probably made to cater to.

 

[3dilettante]

Wel...by definition its a quote. there is not limit in how large a quote has to be to be a quote. they showed something that Wcc said in literal way so its a quote.

And If intel can quote them, so can anyone in the net as well.

Is it fair to say something is a quote if it is heavily modified to give an almost completely opposite meaning to what they said?
It's not a literal copy, pieces were removed with the intent and effect of changing its meaning.

That is all orthogonal to what Wccftech said or whether it is worth quoting.
I've already noted the fallacy of an appeal to authority: "Intel said it, so it must be true"--regardless of the actual value or truth of the thing in question.

Past that objection, it's such a brief statement that it's not really of much substance. It shows no particular synthesis or analysis, so what is being endorsed other than "not much"?

If we skip past that objection, the quote has lost its original meaning due to the editing, so even without judging Wccftech's quality, how is using some of the words they wrote without any of the meaning they had an good endorsement?

Should we skip past that objection, even you said the quote was done to mislead--so how would that be an endorsement for saying Wccftech should be posted here? Wccftech provided the raw material of a dishonest claim, so it's fine to use it in a forum that usually doesn't like dishonest claims? It's a quote by your definition, so they're liars as well?

That's all without getting into the nature of Wccftech, just that Intel's use of a so-called quote doesn't make a case for sourcing from it--or possibly a case for not sourcing from it.


Now as to Wccftech, I generally haven't kept track of it. My impression is that it is unwelcome because this is a forum that does not like low-quality, badly ripped-off, or misleading input. An authority creating misleading noise by badly ripping off text from a different creator of misleading noise doesn't cancel out the noise.


edit:
This seems like the more accurate term and definition:

misquote
verb

1. 1.
   quote (a person or a piece of written or spoken text) inaccurately.
   "the foreign secretary had misquoted Qian"
   synonyms: misreport, misrepresent, misstate, take/quote out of context, distort, twist, slant, bias, put a spin on, falsify
   "my original statement has been misquoted"

 

[Deleted member 2197]

AMD Blogs on Ryzen memory performance
Here’s what they analyzed:

• The impact of the new BankGroupSwap (BGS) BIOS option
• Single-rank DIMMs vs. dual-rank DIMMs
• Automatic sub-timings vs. manually-tweaked subtimings
• Max frequency vs. lower frequency at tighter timings
• Geardown Mode (GDM) on vs. off

http://www.guru3d.com/news-story/amd-blogs-on-ryzen-memory-performance.html

 

[Clukos]

Go figure, I'm running a SR kit at 3466CL14 with tweaked timings and bgs off. No wonder I'm getting good results

 

[xEx]

Is it fair to say something is a quote if it is heavily modified to give an almost completely opposite meaning to what they said?
It's not a literal copy, pieces were removed with the intent and effect of changing its meaning.

That is all orthogonal to what Wccftech said or whether it is worth quoting.
I've already noted the fallacy of an appeal to authority: "Intel said it, so it must be true"--regardless of the actual value or truth of the thing in question.

Past that objection, it's such a brief statement that it's not really of much substance. It shows no particular synthesis or analysis, so what is being endorsed other than "not much"?

If we skip past that objection, the quote has lost its original meaning due to the editing, so even without judging Wccftech's quality, how is using some of the words they wrote without any of the meaning they had an good endorsement?

Should we skip past that objection, even you said the quote was done to mislead--so how would that be an endorsement for saying Wccftech should be posted here? Wccftech provided the raw material of a dishonest claim, so it's fine to use it in a forum that usually doesn't like dishonest claims? It's a quote by your definition, so they're liars as well?

That's all without getting into the nature of Wccftech, just that Intel's use of a so-called quote doesn't make a case for sourcing from it--or possibly a case for not sourcing from it.


Now as to Wccftech, I generally haven't kept track of it. My impression is that it is unwelcome because this is a forum that does not like low-quality, badly ripped-off, or misleading input. An authority creating misleading noise by badly ripping off text from a different creator of misleading noise doesn't cancel out the noise.


edit:
This seems like the more accurate term and definition:

misquote
verb

1. 1.
   quote (a person or a piece of written or spoken text) inaccurately.
   "the foreign secretary had misquoted Qian"
   synonyms: misreport, misrepresent, misstate, take/quote out of context, distort, twist, slant, bias, put a spin on, falsify
   "my original statement has been misquoted"

I think you took it too seriously. I was making a joke because of all the users(with good reasons) said that it should not be allowed to quote/post content from a site like Wccttttscc and now Intel a multi bilion company quote it. It was not a serious claim from my part.

Relax

 

[itsmydamnation]

Were the Anandtech memory latency numbers done for one socket?

Zen's architecture overall does reward a specific level of locality of core activity and memory communication, and Anandtech's preliminary numbers are admitted to be from time-limited testing. Intel's contention that there are going to be inconsistencies in performance whenever a workload doesn't cater to Zen's specific structure and avoids some areas where it is mediocre may be fair. Even workloads that mostly fit in a CCX can suffer from a death by a thousand cuts, and Anandtech does postulate that Zen's higher gain with SMT comes down to it having more performance lost thanks to the poor latency of the subsystem.

Or it could be because Zen is effectively wider then skylake(better distribution of ops over pipes) so being able to sustains 5-6 uops is more likely more often. I think people are missing the forest through the trees. Most servers i see are VMfarms, depending on workload anywhere from 2 to ~6 vcpu over subscription with the most common VM sizes being 2-4 vcpu range. At this kind of over subscription Xeon v2/3/4 have almost always been either I/O bound ( so many shit spec'd SAN's out there) or memory throughput bound. EPYC is going to eat that workload alive, vxrail & nutanix are becoming very popular, we know how well EPYC suites those products. All that is needed is hypervisor awareness of the topology, i bet that will be there day 1 for kvm,xen,esxi,hyperv. To get the best performance out of XCC for this workload you will want to turn on SNC so all this derp from intel is kind of ironic...........


On the DB side most dedicated DB servers are running 10's of DB's, so again just need *sql/oracle to be topology aware for the vast majority of DB's.

At this point you have the vast majority of server market covered, the 4S and massively big SAP HEC make up such a small percentage of CPU count there is no need for AMD to bother at this point. AMD said Naples would meet 80% of server TAM, i think its actually higher.

Zeppelin has even made its way into highend laptops, so this one chip has addressed markets that intel uses 6-7 ( S,H,X(L,M,X) D, Denverton). Now obviously for Zeppelin in every market there is going to be different degrees of trade off, but i challenge anyone else to come up with a more consistent, higher level of performance, bigger TAM for ~$500million and 5 years of engineering effort........

10k employees , 110k employees, 1 chip, 7 chips. AMD have hit most of intels highest margin markets with one chip, if AMD takes market share in enthusiast desktop and server thats going to hurt GP far more then revenue. Thats really going to hurt intel and as a result you see why intel spends 20 odd slides in their product release bagging the competition........

 

[itsmydamnation]

On my last post I was just listen to this

 

[3dilettante]

I think you took it too seriously. I was making a joke because of all the users(with good reasons) said that it should not be allowed to quote/post content from a site like Wccttttscc and now Intel a multi bilion company quote it. It was not a serious claim from my part.

Relax

I apologize if I mistook the tone of the text, it wasn't apparent to me that it was satire. I also didn't recognize the smiley used as being ironic.

Or it could be because Zen is effectively wider then skylake(better distribution of ops over pipes) so being able to sustains 5-6 uops is more likely more often.

If it were more capable of sustaining closer to 5-6 ops in a single-threaded instance, SMT gains would be less--which is probably closer to Skylake's situation based on the broader Ryzen benchmark pool.
The non-unified schedulers would actually work better with SMT since the explicitly independent ops don't run the risk of splitting a thread's dependent operations across multiple schedulers and possibly stalling.

I think people are missing the forest through the trees. Most servers i see are VMfarms, depending on workload anywhere from 2 to ~6 vcpu over subscription with the most common VM sizes being 2-4 vcpu range.

I agree with the general contention that Zen targets a very broad range of the server market well. I think the initial tests may play too well to that generalization, and I'd like to see tests that try to tease out the thresholds and the costs of the uncommon or occasionally inconvenient cases.
The database performance test section was not flattering to Naples, and the author stated on Realworldtech that he will do more followup later. He indicated that synchronization latency is a large contributor.

The Zen architectural choice to not link the pursuit of the server market with the more expensive and difficult to wrangle hardware and infrastructure for wide AVX is likely a strong contributor to why it can keep up despite some strong features with Skylake.
It would take time to roll out a rebalanced high-count CPU that filled the gap that Zen is exploiting, at which time hopefully the next version of Zen has done something to counter the pain points where the monolithic mesh concept is more robust.

 

[Clukos]

If AMD keep the same design for the 7nm shrink the most logical thing to do is to move to 6 cores per CCX, this is how their lineup would look assuming 6 cores per ccx:

Ryzen 7nm (2 ccx)

12 cores (6 per ccx)
10 cores (5 per ccx)
8 cores (4 per ccx)
6 cores (3 per ccx)
4 cores (2 per ccx)

TR 7nm (4 ccx)

24 cores (6 per ccx)
20 cores (5 per ccx)
16 cores (4 per ccx)
12 cores (3 per ccx)

Epyc 7nm (8 ccx)

48 cores (6 per ccx)
40 cores (5 per ccx)
32 cores (4 per ccx)
24 cores (3 per ccx)
16 cores (2 per ccx)
8 cores (1 per ccx)

If that happens, I hope for at least an 8 core/16 thread CPU (with 2 cores disabled per ccx) in the next-gen consoles

 

[fellix]

Whether or not AMD chooses to expand the CCX layout (or cram more quad-core clusters on die), they have to bump up the Infinity Fabric, probably make it asynchronous, so at least the inter-CCX link can work at higher clock-rate, not dependant on the MC speed.

 

[Pressure]

I do believe they should focus on single threaded performance, NUMA (Infinity Fabric) and higher clock speeds for now. The software just isn't there yet for more cores, except in the server and research space. Adding more cores would also just take up more space, which they instead could use to improve a single CCX.

 

[Clukos]

Intel actually put duplicates in their ecosystem "comparison" slide:

Interesting

 

[Clukos]

I do believe they should focus on single threaded performance, NUMA (Infinity Fabric) and higher clock speeds for now. The software just isn't there yet for more cores, except in the server and research space. Adding more cores would also just take up more space, which they instead could use to improve a single CCX.

7nm vs 14nm LPP:

Source: http://www.anandtech.com/show/11558...nm-plans-three-generations-700-mm-hvm-in-2018

Size should be reduced significantly, that is why I think a move to 6 core CCXs is possible. Increased frequency is a given (3.0GHz operation design vs 5.0GHz operation design for servers and data centers). If they want to release a "gaming" consumer CPU aiming for single core perf they could use one 6 core CCX at increased frequency.

 

[entity279]

Intel actually put duplicates in their ecosystem "comparison" slide:

Interesting

Overzeluous and rushed employees did that, rather

 

[hoom]

Intel actually put duplicates in their ecosystem "comparison" slide:

Meanwhile AMD says (in above Scott Aylor presentation) these will have day 1 compatibility

And day 1 server availibility from

Certainly not as much as Intel but a lot of the most important names

 

[Clukos]

Overzeluous and rushed employees did that, rather

Well, the employees are supposed to represent the company. That's why when something like that happens, Intel are to blame, even if the employee responsible ends up getting fired (if Intel didn't specifically order him to add the duplicates in the first place).